Presented by Saion K. Roy and Naresh R. Shanbhag
2:00 PM ET / 11:00 AM PT
Register here: https://ieee.webex.com/weblink/register/raaeddf34787775fb1795d83390102fde
Abstract: Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. To understand the reasons underlying this trend, we develop a behavioral model of resistive IMCs to analyze the signal-to-noise-plus-distortion ratio (SNDR) of MRAM, ReRAM, and FeFET-based IMCs, employing parameter variation and noise models which are validated w.r.t. measured results from a recent MRAM-based IMC prototype in a 22nm process. We obtain fundamental limits on the maximum achievable SNDR under various operating conditions and identify device and circuit parameters that have the most significant impact on the SNDR. Finally, we study the impact of bank level SNDR on network-level accuracy by mapping ResNet-20 (CIFAR-10) to find that MRAM and FeFET-based architectures find it challenging to meet the minimum SNDR required for the classification accuracy to approach that of a fixed-point digital architecture – a result that clearly implies the need for algorithmic and learning-based methods, to improve the inference accuracy of resistive IMC architectures. Next, we hypothesize that the low native SNDR of resistive IMCs might provide resilience against security attacks, such as model extraction attacks (MEAs). This hypothesis is invalidated by employing the behavioral model to develop resistive IMC-specific MEAs, which are then applied to the 22nm MRAM-based IMC prototype and shown to be quite effective in extracting model weights. The security vulnerability of resistive IMCs is shown to be a function of the SNDR, and the trade-off between energy-accuracy-security of resistive IMCs is quantified. This work opens up opportunities for AI chip designers and security experts to design resistive IMCs that are secure, energy-efficient, and accurate.
Bios:
Saion K. Roy Saion K. Roy (Member, IEEE) received his Ph.D. from the University of Illinois at Urbana–Champaign, USA, in 2024, and his B.Tech. and M.Tech. degrees from the Indian Institute of Technology Kharagpur, India, in 2018. His research interests encompass energy-efficient integrated circuit design and analysis, with a focus on eNVM-based in-memory computing architectures for machine learning (ML) algorithms. He is currently a postdoctoral researcher at Northeastern University, where he is focusing on the security vulnerabilities of ML accelerators. His Ph.D. research resulted in publications in venues such as ESSCIRC, CICC, IEDM, ICCAD, JSSC, and JxCDC. He has also been a reviewer for JETCAS, TVLSI, and JSSC.
Naresh R. Shanbhag Naresh R. Shanbhag (Fellow, IEEE) received the Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, MN, USA, in 1993. He is currently the Jack Kilby Professor of Electrical and Computer Engineering with the University of Illinois at Urbana-Champaign, Champaign, IL, USA. From 1993 to 1995, he was with AT&T Bell Laboratories, Murray Hill, NJ, USA, where he led the design of high-speed transceiver chip-sets for very high-speed digital subscriber line, before joining the University of Illinois at Urbana-Champaign in August 1995. He has held visiting faculty appointments with National Taiwan University, Taipei, Taiwan, during August–December 2007 and Stanford University, Stanford, CA, USA, during August–December 2014. He holds 13 US patents, is the coauthor of two books and multiple book chapters, and more than 200 publications in his research field, which include the design of energy-efficient systems for machine learning, communications, and signal processing, spanning algorithms, architectures, and integrated circuits. Dr. Shanbhag was the recipient of the 2024 SRC Innovation Award, the 2018 SIA/SRC University Researcher Award, the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lecturership in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards including the 2006 IEEE Solid-State Circuits Society Best Paper Award. In 2000, he co-founded and was the Chief Technology Officer of the Intersymbol Communications, Inc., which introduced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links and was acquired by Finisar Corporation in 2007. From 2013 to 2017, he was the Founding Director of the Systems on Nanoscale Information fabrics Center, a five-year multi university center funded by DARPA and SRC under the STARnet Program. Since Since 2023, he is leading research themes in the SRC and DARPA funded JUMP 2.0 Program’s Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity.