Terms through 30 April 2028
Biography: Po-Hung Chen received the M.S. degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2007, and the Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 2012. In 2011, he was a Visiting Scholar with the University of California at Berkeley, Berkeley, CA, USA, where he conducted research in fully integrated power management circuits for RISC-V processors.
He is currently a Professor with the Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. His research interests focus on power management integrated circuits, with a special emphasis on energy harvesting, power supply unit, point-of load regulators, and wireless power transmission.
Dr. Chen has been a Technical Program Committee Member of the IEEE Symposium on VLSI Circuits since 2020. He was the TPC Vice-Chair of A-SSCC 2020 and a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is also the Vice Chair of the IEEE Solid-State Circuits Society Taipei Chapter.
Presentations:
Energy Harvesting Integrated Circuits for Battery-free IoT Devices
Abstract: This talk presents a state-of-the-art energy harvesting integrated circuit designed for battery-free IoT devices powered by ambient energy sources. It discusses key circuit design considerations for a single-inductor, multi-source, multi-output (SIMSMO) converter capable of interfacing with diverse energy transducers.
The presentation highlights efficient techniques for extracting energy under widely varying voltage, current, and impedance conditions, as well as the challenges of sequential power delivery and output regulation in low-power environments. An adaptive peak-inductor-current control scheme is introduced to dynamically adjust the inductor current according to operating conditions, effectively suppressing output voltage ripple while maintaining high conversion efficiency across wide input and output voltage ranges.
Close-Loop Active Gate Driver ICs for SiC Power MOSFETs
Abstract: This talk presents a universal active gate driver (AGD) integrated circuit for silicon carbide (SiC) MOSFETs. While SiC devices enable high efficiency and power density, their fast switching often causes voltage overshoot, oscillation, and electromagnetic interference (EMI) due to parasitic elements.
A gate-voltage sensing technique is introduced to detect switching dynamics directly from the gate terminal, removing the need for external current or drain-voltage sensing. By monitoring transient gate behavior during high di/dt intervals, the AGD identifies critical switching moments and adaptively adjusts its driving strength to suppress overshoot and oscillation while maintaining low switching loss. The closed-loop AGD integrates sensing and adaptive driving into a fully on-chip solution compatible with various SiC MOSFETs.
High-Efficiency Wireless Power Transfer Techniques
Abstract: This talk introduces circuit and system techniques for improving the efficiency of inductive wireless power transfer (WPT) systems for battery-less applications. By using wireless feedback from the receiver, the transmitter operation can be adjusted to better match load demand, reducing unnecessary power transfer.
On the receiver side, rectification and regulation approaches that store and reuse excess received energy are discussed to enhance efficiency under varying coupling and load conditions. Prototype implementations with integrated data communication demonstrate practical methods for achieving efficient and reliable wireless power delivery.
Biography: Dr. Sijun Du received a B.Eng. degree (honors) in electrical engineering from the University Pierre and Marie Curie (UPMC), Paris, France, in 2011, and an M.Sc. degree (distinction) in electrical and electronic engineering from Imperial College, London, U.K., in 2012. He started his Ph.D. research in October 2014 and obtained his Ph.D. degree in electrical engineering from the University of Cambridge, Cambridge, U.K., in January 2018. He was a postdoctoral researcher at the Department of Electrical Engineering and Computer Sciences (EECS), University of California, Berkeley, CA, U.S.A., from 2018 to 2020. In 2020, he joined the Department of Microelectronics, Delft University of Technology (TU Delft), Delft, the Netherlands, as an associate professor. His current research is focused on energy-efficient integrated circuits and systems, including power management integrated circuits (PMIC), energy harvesting, wireless power transfer, and DC/DC converters.
He received the Dutch Research Council (NWO) Talent Program VENI grant in the 2021 round, the Best Student Paper Award in IEEE ICECS 2022, and the SSCS Reviewer Award in 2024 and 2025. He is an IEEE SSCS Distinguished Lecturer from 2026 to 2027. He serves as a technical program committee (TPC) member of IEEE ISSCC, IEEE ESSERC, and ISSCC Student Research Preview (SRP). He served as the IEEE ICECS sub-committee chair in 2022 and 2024, and the IEEE ISCAS sub-committee chair in 2025 and 2026. He is an IEEE Senior Member.
Presentations:
Miniaturized and High-Efficiency Piezoelectric Energy Harvesting ICs for Self-Powered IoT Systems
Abstract: The Internet of Things (IoT) is rapidly expanding, relying on a massive number of distributed wireless sensors that bridge the physical and digital worlds. Powering these sensors with conventional batteries is often impractical due to the prohibitive effort and cost of replacement or recharging at large scale. Harvesting energy from ambient vibrations, particularly using piezoelectric transducers, has therefore emerged as a compelling alternative for enabling self-sustained operation. However, limited available power and strict cost constraints make efficiency and integration key design challenges. This talk reviews recent advances in piezoelectric vibration energy harvesting integrated circuits, with emphasis on high-efficiency rectification techniques, inductor-less voltage-flipping architectures, and fast maximum power point tracking (MPPT) schemes for both periodic and shock excitations. Circuit solutions that enhance energy extraction while reducing off-chip components are presented, highlighting pathways toward compact, fully integrated, and cost-effective power solutions for next-generation IoT systems.
Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter
Abstract: Switched-capacitor (SC) DC-DC converters make on-chip voltage conversion possible but are only effective at a few voltage conversion ratio (VCR) points. A new SC converter type called continuously scalable conversion-ratio (CSCR) SC was developed to operate across a continuous VCR range. In this talk, the invention, development, applications, and future of the CSCR SC will be discussed. Its topology and working principle will be introduced first, followed by the fundamental differences and benefits compared with traditional SC designs. It was first implemented as a buck converter and later extended to boost and buck-boost versions. VCR extension techniques, such as intermediate-rail reconfiguration, input-rail splitting, and stacking architecture, have made it applicable to solar and thermoelectric energy-harvesting interfaces.
High-Density Capacitor-First AC/DC Converters for Compact and Efficient IoT Power Delivery
Abstract: As IoT devices continue to proliferate in smart homes and industrial environments, there is a growing demand for compact, safe, and energy-efficient power supplies directly from 110/220V AC mains. Conventional AC/DC solutions often rely on bulky magnetic components or suffer from poor efficiency at low-to-medium power levels, limiting their suitability for highly integrated systems. This talk introduces capacitor-first AC/DC interface techniques that enable high power density, reduced standby loss, and strong integration capability while maintaining safety and robustness. By rethinking how high-voltage energy is processed and regulated, these approaches achieve efficient power delivery from milliwatt to watt levels in compact form factors. The presented solutions offer a scalable and cost-effective pathway toward high-performance AC-powered IoT systems.
Inductive Wireless Power Transfer Design for Miniature Biomedical Implants
Abstract: Inductive wireless power transfer (WPT) has become a key enabling technology for miniature biomedical implants, providing a non-invasive and reliable power source for neural interfaces, retinal prostheses, and other implantable devices. However, stringent size constraints, fluctuating coil coupling, multi-voltage supply requirements, and tissue safety considerations make system design highly challenging. This talk presents a comprehensive overview of inductive WPT architectures from transmitter (TX), receiver (RX), and system perspectives. Design strategies to address coupling variation, extend voltage conversion ratio (VCR) under weak links, and maintain high power conversion efficiency are discussed. Both local output regulation at the RX and global regulation across the TX–RX link are examined, along with approaches for multi-output generation.
Piezoelectric Resonator-Based DC-DC Converters: An IC Design Perspective
Abstract: Piezoelectric resonators (PRs) are emerging as a potential alternative to magnetic components in miniaturized power conversion, offering high energy density and favorable scaling properties. They open interesting opportunities to rethink how energy storage and voltage conversion can be realized in compact and highly integrated systems. Unlike conventional LC-based designs, PR-based converters rely on electromechanical resonance and exhibit distinctive impedance characteristics, which influence topology selection, operating modes, and control strategies. This talk presents an overview of PR-based DC-DC converters from an IC design perspective. The fundamental operating concepts are introduced, followed by a discussion of representative converter structures and regulation approaches. On-chip timing control, soft switching, integration challenges, and system level co-design between the piezoelectric component and CMOS circuits will be discussed. The aim is to provide a broad framework for understanding this emerging direction and its implications for future integrated power management.
Biography: Chih-Cheng Hsieh received his B.S., M.S., and Ph.D. degrees in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan. From 1999 to 2007, he was with PixArt Imaging Inc., where he led mixed-signal IC development for CMOS image sensor products in consumer and mobile applications. He is currently a Full Professor in the Department of Electrical Engineering at National Tsing Hua University, Taiwan.
His research focuses on intelligent sensing and data converters, including smart CMOS image sensors, processing-in-sensor (PIS) architectures, and high-resolution, high-speed, and energy-efficient ADCs. His work spans a wide range of applications such as imaging, sensing, communications, and mixed-signal systems. Dr. Hsieh has served on the A-SSCC and ISSCC Technical Program Committees. He has also been an invited forum and tutorial speaker at major solid-state circuits conferences.
Presentations:
Inside CMOS Image Sensors: From Pixels to System-Level Design Trade-offs
Abstract: CMOS image sensors are highly integrated mixed-signal systems in which pixel architecture, readout circuits, and ADC design jointly determine performance. This lecture presents a circuit-level view of CMOS image sensors, covering photodiodes, pixel structures, noise mechanisms, shutter operation, and column-parallel readout. Key trade-offs among conversion gain, noise, dynamic range, power, and cost are discussed, providing practical insights for imaging and sensing IC designers.
Processing-in-Sensor: Circuit Techniques for Intelligent and Energy-Efficient Vision
Abstract: Processing-in-Sensor (PIS) integrates feature extraction and early processing directly within image sensors to reduce data bandwidth, power consumption, and latency. This lecture surveys PIS architectures from in-pixel to in-column and near-sensor processing, and discusses spatial- and temporal-domain feature extraction from a circuit design perspective. The talk highlights how mixed-signal in-sensor computing enables always-on and energy-efficient intelligent vision systems.
Application-Driven ADC Design: Enabling Sensors and Edge AI Systems
Abstract: ADCs are key interfaces between the analog physical world and digital intelligence, especially in power-constrained sensing and edge AI applications. This lecture focuses on application-driven ADC design, reviewing low-power SAR ADC architectures and energy-efficient techniques at circuit and architecture levels. Examples from sensing and IoT systems illustrate how relaxed precision and application-aware design lead to significant system-level efficiency improvements.
Biography: Thomas Lee received his degrees from MIT, where his 1989 thesis described the first CMOS radio. He established the Stanford Microwave Integrated Circuits Laboratory in 1994, after having worked at Analog Devices, Rambus and other companies. He's designed PLLs for microprocessors, and co-founded Matrix Semiconductor, among others.
He is a Ho-Am (Samsung) Prize laureate; an IEEE and Packard Foundation Fellow; a two-time ISSCC "Best Paper" awardee; and recipient of an Honoris Causa doctorate from U. of Waterloo (2013) and the 2021 IEEE Gustav Kirchhoff award. He was awarded a U.S. Secretary of Defense Medal (2012) for his work as Director of DARPA's MTO, and served as a Director at Xilinx up to its acquisition by AMD in 2022.
He continues to serve on the boards of several companies and owns thousands of vacuum tubes, hundreds of oscilloscopes, and countless obsolete semiconductors. No one, especially himself, quite knows why.
Presentations:
Compute-Energy Scaling Will Stimulate a New Wave of Innovation
Abstract: The exponential growth in global compute-energy can't continue for even a couple more decades. Future computers will have to be more powerful without being more power-hungry, but our "trick bag" is nearly empty. Solving this problem will necessarily stimulate transformative creativity. This talk will discuss some possible ways to get to the future without boiling the earth.
Dark Secrets from the World of Instrumentation
Abstract: Engineers rely on instruments to tell them what their circuits are doing. That means that the instruments have to exhibit better performance than the devices under test. Instrumentation engineers thus have the supremely difficult task of providing tomorrow's performance using today's technology. That pressure has stimulated tremendous creativity, not all of which is appreciated widely, if at all. This talk will examine the circuits of a few iconic products, including HP's 200A Wien-bridge oscillator (and Hewlett's design error), the 100MHz Tektronix 465 oscilloscope, and the 1GHz Tektronix 7104 oscilloscope (the fastest purely-analog oscilloscope ever put into volume production). If there is interest (and if time permits), other instruments and their circuit tricks will be presented as well.
From Rocks to Chips: Stories of the Transistor and its Future
Abstract: The discovery, then invention, of the transistor sits almost exactly midway between Ferdinand Braun's discovery of solid-state rectification in 1874 and the modern era of gigascale ICs. As with other epoch-shattering inventions, the story of the transistor isn't quite as neatly linear as some recountings might suggest. Very few EEs have ever heard of Mervin Kelly, although we all owe our jobs to him. This talk will try to right that wrong, as well as answer questions such as, "What was a point-contact transistor? What happened to germanium devices? What really led Noyce to create the planar integrated circuit?" Retracing some of the steps of the pioneers and their motivations generates important insights into the nature of innovation, and teaches us valuable lessons about the role of a very few visionaries and a great deal of luck. With the end of lithographic scaling, we find ourselves on the threshold of a major technological discontinuity. Studying the story of previous ones just might provide us with our best guide to the future.
Go Big or Go Home: The First Transatlantic Telegraph Cable and the Troubled Birth of EE
Abstract: Electrical engineers are the children of a failure so colossal and traumatic that we don't even talk about it. American paper magnate Cyrus West Field decided one day in the 1850s to span the Atlantic with a telegraph cable; it was the Victorian era's moon-shot. Amplifiers would not exist for another half-century, so success would require mastery of technologies not yet developed. Regrettably, the project's technical head was a medical doctor, so tragic hilarity ensued. A British board of inquiry convened to assess the inevitable disaster noted that the "electrical arts" lacked a vocabulary even to describe the failure quantitatively. William Thomson was eventually named the new technical lead, and drove the project to final success in 1866. The volt, ohm and ampere were formally defined shortly thereafter and the profession of electrical engineering was born. Thomson -- arguably the first professional electrical engineer -- became Lord Kelvin, and EEs have been busy making mischief ever since.
Biography: Antonio Liscidini received a Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying polyphase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit design. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently Full Professor and Associate Chair Graduate. From 2019 to 2022 he was consultant for Huawei Technology Group in the area of RFIC for optical communication and SerDes. Since 2022 has been consultant for Marvell Technology group. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless-wireline communication and ultra-low power applications.
Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits, co-recipient of the Best Invited Paper Award at the 2011 IEEE CICC and Best Student Paper Award at the 2018 IEEE ESSCIRC.
He is currently Associate Editor in Chief for IEEE Transactions on Circuits and Systems II: Express Briefs and Associate and IEEE Solid State Circuit Letters. He has served as an Associate Editor for Editor for IEEE Open Journal of Solid-State Circuit Society, IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and IEEE RFIC Virtual Journal (2018). He has been member for many conferences including ISSCC, ESSCIRC, and CICC. Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. Since 2026, he is a IEEE Fellow.
Presentations:
Quantized-Analog Signal Processing
Abstract: Today, both digital and analog electronics are hitting fundamental limits that demand revolutionary approaches to meet the power/bandwidth demands of the next generation of data-driven applications. One of these new approaches is the quantized analog signal processing that merges analog and digital domains more fluidly than traditional mixed-signal circuits, eliminating the need for rigid interfaces like analog-to-digital and digital-to-analog converters.
In the first part of the talk, we’ll compare analog and digital signal processing in terms of power efficiency. We’ll highlight a thermodynamic upper bound that relates dynamic range, bandwidth, and power dissipation. To overcome this limit, we’ll introduce quantized-analog signal processing in the second part.
We’ll demonstrate that quantized-analog signal processing offers superior power efficiency and flexibility compared to its analog counterpart, making it a promising candidate for developing a new generation of mixed-signal integrated circuits. The effectiveness of our proposed solutions will be shown through simulations and measurement results.
Trends in Analog Mixed Signal Circuits from 5G to AI
Abstract: In this talk, we’ll delve into some fundamental aspects of signal processing to understand how they will shape the future of IC mixed-signal design. In the first part of the lecture, we’ll compare power efficiency and technology evolution, discussing the dualism of analog/digital and voltage/time in terms of signal processing and dynamic range achievable.
In the second part of the presentation, we’ll explore two examples of how analog mixed-signal can achieve the flexibility of digital signal processing while maintaining higher speed and power efficiency of analog. We’ll present a novel topology of a MAC analog accelerator for digital computation in AI and a quantized analog TX for 5G wireless communication that exploits a power-scalable band-pass RF DAC. These solutions outperform the state of the art and suggest new directions for future development in mixed-signal computation and software-defined analog front-ends.
Presentations:
Title: Calibration of high speed, high performance digital-to-analog converters Abstract: Traditional calibration techniques are effective at compensating for static nonidealities. However, as clock rates and signal frequencies continue to increase, dynamic errors have become increasingly significant contributors to output spectral purity. Direct measurement of these dynamic error sources is not only extremely challenging, but can also exacerbate the errors themselves. In response, recent years have seen the emergence of new approaches focused on assessing the impact of dynamic errors and actively mitigating them, yielding promising results. Simultaneously, time-interleaved DACs (TI-DACs) are gaining traction. While many of the challenges faced by TI-DACs are similar to those encountered with time-interleaved ADCs (TI- ADCs), the correction or calibration of time-interleaving errors in TI-DACs often must be performed in the analog domain, presenting a unique set of challenges. This presentation provides an overview of some of the most interesting and innovative recent developments in this area. Title: A perspective on Analog and Mixed-Signal IC design amid Semiconductor Paradigm Shifts Abstract: In this talk, a forward-looking perspective on strategies for advancing analog and mixed-signal (AMS) IC design is presented. It is argued that the traditional paradigm of isolated, transistor-level sub-block optimization is increasingly inadequate for the stringent power and performance demands of contemporary communication systems and emerging AI applications. Instead, the industry requires a critical shift toward "full-stack" solutions. This demands comprehensive system-level analysis and cross-layer innovation, breaking down established boundaries of design abstraction to minimize physical resources and overall complexity. Drawing on concrete design examples, the practical benefits and drawbacks of this holistic methodology are illustrated.
Biography: Sanu K. Mathew (M’99, SM-‘15, F-‘18) is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he heads the security arithmetic circuits research group, responsible for developing energy-efficient computer arithmetic data-path circuits and special-purpose hardware accelerators for cryptography and security. He has over 27 years of experience in high-performance SOC design in leading-edge semiconductor process technologies and has delivered cryptographic engines to multiple generations of Intel security technologies, including AES-NI, SGX, MKTME, PCLMULQDQ, SHA-NI, GFNI, TRNG and PUF technologies.
Since 2015, his research has focused on developing countermeasures against physical side-channel and fault-injection attacks on security hardware technologies. He also drives research and development of post-quantum crypto, light-weight crypto and fully-homomorphic encryption hardware. He is a recipient of two Intel Achievement Awards (Intel Corporation’s highest technical award), Intel Labs Gordon Moore Award, Distinguished paper award from IEEE International Solid State Circuits Conference, Outstanding industry mentor award from Semiconductor Research Corporation and the Best paper award from IEEE European Solid State Circuits Conference.
He was recognized as a top contributor in IEEE International Solid State Circuits Conference’s 70 years publication history. He has filed over 148 patents and has published 95 conference/journal papers and authored 2 book chapters. He also mentors Intel & SRC-funded research projects in leading universities and serves as an Associate Editor of the IEEE Journal of Solid-State Circuits. He has also served on the technical program committees of the ISSCC, ARITH, ISLPED, DAC and SOCC conferences. He is a Fellow of the IEEE.
Dr. Mathew received the B.Tech. degree in Electronics and Communications Engineering from College of Engineering, Trivandrum, India in 1993, followed by M.S and Ph.D. degrees in Electrical and Computer Engineering from State University of New York at Buffalo in 1996 and 1999 respectively. He has been with Intel Corporation since 1999.
Presentations:
Attack-resistant Cryptographic Hardware Accelerators for Secure Platforms
Abstract: Secure platforms rely on silicon-embedded root-of-trust circuits to deliver security guarantees, while operating in hostile environments where adversaries are present at all layers of the compute stack. Attackers employ a variety of attack modalities using side-channels (SCA) and fault-injection (FIA) to steal on-die secret keys/IDs. In this talk, we will discuss how attackers mount SCA and FIA on symmetric-key and public-key encryption engines and explore various countermeasures against such attacks that offer different levels of protection and incur a range of area and performance overheads. The talk will describe the design of a reconfigurable AES engine that operates in SCA-resistant mode in a hostile environment, while allowing the administrator to switch to a high-performance mode while operating in a secure environment. We will also discuss the design of a self-checking AES engine that detects malicious injected faults in real-time using checker circuits.
Entropy Generation Circuits for Secure Root-of-Trust: True Random Number Generators and Physically-Unclonable-Functions
Abstract: Silicon-embedded root-of-trust circuits such as True Random Number Generators (TRNG) and Physically Unclonable Functions (PUF) are foundational primitives that generate dynamic and static entropy essential for data security and privacy applications. This talk will describe all-digital area-efficient implementations of TRNGs and PUFs that generate cryptographic quality random bitstreams with tolerance to process/voltage/temperature variations, including: (a) An all-digital TRNG with built in self-calibrating feedback loop with two-step coarse/fine-grained tuning achieving robust operation in the presence of 20% process variation while providing immunity to run-time voltage and temperature fluctuations. The 100% digital design enables a compact layout with measured entropy of 0.999965, and scalable operation down to 280mV, while passing all NIST RNG tests. (b) Hybrid Physically Unclonable Function (PUF) circuit that leverages burn-in induced aging to reduce bit-errors, followed by temporal-majority-voting, dark-bit masking, and error-correction conditioning techniques to generate a 100% stable full-entropy key an ultra-low energy consumption (c) Unified PUF-TRNG with a common-entropy source and self-calibrating Von Neumann extractor circuits generating PUF/TRNG random bit throughput of 0.56/1.48Gbps with 0.9996/0.99997 static/dynamic entropy respectively.
Chips to Accelerate Fully-homomorphic Encryption (FHE) are here: HERACLES, An 8192-Way SIMD Programmable Scalable Fully-Homomorphic Encryption SoC for Privacy-Preserving Cloud Computing in Intel 3 CMOS
Abstract: Fully homomorphic encryption (FHE) is regarded as the holy-grail of secure private computing, enabling arbitrary computations on encrypted data without requiring users to share their secret keys with untrusted third parties. Unlike classical cryptographic schemes such as advanced encryption standard (AES), that protect data only during transmission and storage, FHE extends confidentiality to the computation phase itself, preserving data privacy on untrusted infrastructure, making FHE a foundational technology for privacy-preserving cloud computing. However, FHE poses significant challenges that make real-time interactive execution infeasible on present-day systems, including ~105× increase in ciphertext sizes, massively parallel modular arithmetic and complex wide-vector permutations. While special-purpose FHE accelerators have been previously reported, they lack support for bootstrappable parameters [2], have limited ondie memory [2-4] leading to off-chip communication bottlenecks, or employ separate number-theoretic-transform (NTT), MAC, and automorphism modules resulting in complex data movement scenarios [2-5]. This talk will go over the challenges of building hardware accelerators for FHE and present HERACLES: The world’s first FHE SOC-of-scale fabricated in Intel 3 CMOS, with single-cycle 8k polynomial arithmetic throughput using a massively-parallel 8192-way SIMD vector compute engine. The programmable scalable SoC employs a 3-tiered memory subsystem, optimized Cooley-Tukey NTT/iNTT butterflies and a 2D mesh NoC to support multiple FHE schemes and parameters, with measured compute engine throughput of 29.49TOPs at 0.75V, 1.2GHz, delivering up to 5547× higher FHE performance than general-purpose CPUs.
Biography: Dr. Sengupta is an IEEE Fellow and currently Professor in the department of Electrical and Computer Engineering at Princeton University. He received a B.Tech/M.Tech (dual degree) in Electronics and Electrical Communication Eng. from the Indian Institute of Technology, Kharagpur, in 2007, an M.S. in Electrical Engineering from Caltech in 2008, and a Ph.D. in Electrical Engineering from Caltech in 2012.
His research interests include novel chip-scale architectures for intelligent sensing and communication for a wide range of emerging applications. Dr. Sengupta is an IEEE Fellow. He received the DARPA Young Faculty Award in 2018, the Bell Labs Prize in 2017, the Young Investigator Program Award from the Office of Naval Research in 2017, the Prime Minister Gold Medal Award from IIT Kharagpur in 2007, the Charles Wilts Prize at Caltech for the best Electrical Engineering Ph.D. thesis in 2013, and the inaugural Young Alumni Achievement Award from IIT Kharagpur in 2018.
He served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society from 2019 to 2020 and for the IEEE Microwave Theory and Technology Society from 2021 to 2023. He is a recipient of the 2021 IEEE Microwave Theory and Technology Outstanding Young Engineer Award and the 2022 IEEE Solid-state Circuits New Frontier Award. He received the IEEE Microwave Prize in 2015, several best paper awards including IEEE IMS (2020, 2021, 2022, 2025), RFIC (2012), and the Best paper of the year award from IEEE Journal of Solid-State Circuits in 2023 for the first deep-learning enabled RFIC design.
Presentations:
AI-enabled RFIC Design beyond Human Intuition
Abstract: Traditionally, chip-scale RF system design has been in the domain of the expert, dominated by thumb rules and trial and error techniques. Designing these ICs, that form the bedrock of the wireless networks, is complex, time-consuming, requires years of expertise, and therefore, can be very expensive. Historically, the design process of RF IC design has relied on intuition based approaches with standard templates that are subsequently optimized, time-consuming parameter sweeps, or ad-hoc population-based metaheuristic optimization methods. There is no reason to believe that this approach is optimal in any sense. This talk will discuss how inverse design with AI-based approaches can open a new design space and allow rapid designs on demand. It will discuss deep-learning based modeling and generative AI approaches, that are transferrable across process design technologies, for inverse design and automated synthesis of mmWave/sub-THz circuits and antennas.
Scalable and Tileable Millimeter-Wave and Terahertz Surfaces for Ultra-Large-Scale Communication and Sensing Systems
Abstract: Millimeter-wave (mmWave) and terahertz (THz) arrays are traditionally built using active transceivers connected to antennas through complex beamforming networks. While effective, this approach becomes increasingly challenging as systems scale to very large apertures for satellite communications, next-generation wireless infrastructure, and advanced sensing. This talk presents an alternative paradigm based on scalable, tileable active metasurfaces implemented using CMOS-integrated chips directly coupled to antenna arrays. These programmable reflect–transmit surfaces enable electronic beam steering, wavefront shaping, and amplification while significantly simplifying array scalability. Design considerations, circuit–antenna co-integration, and applications in non-line-of-sight sensing and high-frequency communication systems will be discussed.
Biography: Jae-sun Seo is an Associate Professor at the ECE department at Cornell Tech since July 2023, before which he was an Associate/Assistant Professor at Arizona State University since 2014. He was a visiting researcher at Meta Reality Labs from 2022 to 2023, and he worked at IBM T. J. Watson Research Center from 2010 to 2013.
His research interests include efficient ASIC and FPGA hardware design of machine learning algorithms and neuromorphic computing. Dr. Seo was a recipient of the 2012 IBM Outstanding Technical Achievement Award, 2017 NSF CAREER Award, 2020 Intel Outstanding Researcher Award, and 2022 IEEE TVLSI Best Paper Award. He has served on the technical program committees for ISSCC, ESSERC, ISCA, HPCA, MLSys, DAC, DATE, etc.
Presentations:
Recent Digital Compute-In-Memory Designs with Various Precision/Sparsity Schemes and SoC-level Evaluation
Abstract: This talk will present the recent landscape of digital compute-in-memory (CIM) designs for AI applications from my research group and the literature. It will feature digital CIM macro chip designs with sparse computing using compressed weights, low-to-high precision support, and different number formats including integer, floating-point, and microscaling. While high energy-efficiencies have been reported at the CIM macro levels, it is important to evaluate the energy-efficiency of CIM based accelerators at the system-on-chip (SoC) level for practical system considerations. We present collective benchmarking framework development efforts for 2D SoC and 3D IC designs, showcasing the benefits and considerations of CIM designs at the system level.
Biography: Shahriar Shahramian received his Ph.D. degree from the University of Toronto in 2010, where his research focused on mm-wave data converters and transceivers. He joined Bell Laboratories, Nokia, in 2009 and is currently Director of the Integrated Circuits & Microsystems Research Lab. His research program addresses the design of next-generation wireless, optical, and sensing systems. Shahriar and his team have made seminal contributions to the design and industrialization of mm-wave phased arrays, sub-THz communication links, and high-speed optical devices. In addition, his lab has demonstrated high-performance organic- and glass-based packaging technologies with unprecedented integration & electrical performance.
Shahriar was elevated to Bell Labs Fellow in 2020. Shahriar has served as a subcommittee chair and member of the technical program committees of several IEEE conferences, including the International Solid-State Circuits Conference (ISSCC), the Radio Frequency Integrated Circuits Symposium (RFIC), and the BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). He has also served as a Guest Editor of the IEEE Journal of Solid-State Circuits. He is a frequent contributor to IEEE workshops, tutorials, and technical forums. Shahriar and his team have received multiple IEEE Best Paper Awards, and he is the recipient of the IEEE MTT Young Engineer Award (2020). He was elevated to IEEE Senior Member in 2020 and IEEE Fellow in 2026.
Shahriar holds Adjunct Associate Professor appointments at Columbia University and Princeton University, has received multiple teaching awards, and is the founder & host of The Signal Path educational video series (https://www.TheSignalPath.com). His freely available in-depth educational videos, which cover a wide range of electrical engineering & metrology topics, have received over 12 million views.
Presentations:
The Art of Metrology – Measurement Techniques & Pitfalls
Abstract: Despite the central role of instrumentation in electrical engineering, metrology techniques, and their common pitfalls, are often underemphasized in university curricula. Inaccurate measurements can undermine a researcher's credibility and lead to costly setbacks, potentially amounting to millions of dollars during product development and commercialization. At the same time, instrumentation technologies have advanced rapidly, blurring the boundaries between measurement domains. This progress, however, has introduced new challenges: increasing complexity in measurement setups, abstraction of instrument functions, and limited user experience frequently contribute to misleading or erroneous characterizations.
This lecture explores frequency-, time-, and mixed-domain measurements, with particular emphasis on noise figure, phase noise, broadband modulation, sub-THz signal detection, eye-diagram capture, and frequency conversion behavior. These topics will be examined through the lens of diverse instrumentation architectures that enable such measurements ranging from DC to optical characterization. Additionally, we will highlight the precision, accuracy, repeatability, and resolution limits of various instruments to underscore the importance of uncertainty quantification, error bars, and robust fault detection.
The Art of Semiconductor Layout – mm-Wave & High-Speed Layout Techniques & Pitfalls
Abstract: We live in the golden age of high-speed & mm-wave ASIC design! Next generation optical & wireline communications, mm-wave & sub-THz wireless links as well as next generation high-resolution radars all demand integrated circuits & packages operating beyond 100GHz. Despite the ubiquitous need for such devices, mm-wave layout techniques are rare and highly sought after expertise.
This lecture explores the hidden impairments which are often overlooked or difficult to locate in mm-wave layouts and interconnects. Using real-life fabricated circuit blocks operating up to and beyond D-band (170GHz) as well as optical circuits operating beyond 100Gb/s you are invited to search for layout challenges and impairments which can adversely affect the circuit performance. After modeling these elements, simulations demonstrate the impact of the parasitics on bandwidth, center frequency, stability, and noise figure. Using simple and quick modeling techniques, the designers can incorporate effects of various layout parasitics. Furthermore, mm-wave techniques at chip level are explored from ground planes to flip-chip bumps. Finally, we expand our views beyond the boundaries of integrated circuits and explore co-design techniques to carry mm-wave signals into packages, printed circuit boards, glass interposers & antennas.
Presentations:
Learning to Think Like a Circuit Designer: Circuit Intuitions and Insights
Abstract: Modern integrated-circuit design is built upon a vast body of theory, models, and design methodologies. Yet, many of the most powerful ideas in circuit design are best understood through intuition developed from experience rather than through equations alone. Over the years, a collection of short articles titled Circuit Intuitions in the IEEE Solid-State Circuits Magazine, together with the Circuit Insights educational events organized at major conferences, has explored a wide range of concepts aimed at developing this intuition. This DL talk is designed as a flexible, interactive session that can be tailored to the interests of the hosting SSCS chapter. The presentation may draw on selected topics from the Circuit Intuitions series or from past Circuit Insights talks, covering concepts such as looking into a node, noise and distortion, device-level insights for circuit designers, and other foundational ideas in analog and mixed-signal design. The talk is primarily intended for senior undergraduate students, starting graduate students, and early-career circuit designers, though it is also suitable for experienced engineers who enjoy revisiting fundamental ideas from a fresh perspective. By focusing on visual explanations, simple thought experiments, and intuitive reasoning, the goal is to reveal the physical and conceptual insights that often lie hidden beneath familiar circuit equations.Understanding Jitter and Phase Noise: From Fundamentals to High-Speed Wireline Systems
Abstract: Jitter and phase noise are fundamental performance limitations in modern high-speed communication systems, yet they are often perceived as difficult concepts due to the many ways they are defined, measured, and specified. This talk provides an intuitive and unified understanding of jitter and phase noise, connecting the physical origins of timing fluctuations to the metrics used in practical system design. Starting from basic concepts, the presentation explains how noise sources translate into timing uncertainty in oscillators, clocking circuits, and communication links. The relationships between phase noise, time-domain jitter, and common industry metrics are developed using simple graphical and conceptual explanations. Particular emphasis is placed on high-speed wireline systems, where jitter directly limits data rates and link reliability. Drawing on material from the textbook Understanding Jitter and Phase Noise, the talk discusses practical issues such as jitter generation, jitter transfer through phase-locked loops, jitter tolerance, and the impact of jitter on bit-error rate.Limits of Signaling in Wireline Communication
Abstract: High-speed wireline communication systems have advanced dramatically over the past several decades, pushing data rates on copper channels to hundreds of gigabits per second. Yet these impressive achievements raise a fundamental question: how far can we ultimately go with electrical signaling over copper? This talk explores the fundamental limits of wireline communication by starting from first principles and gradually connecting theory to practical circuit and system design. Beginning with Shannon’s channel capacity, the presentation examines how channel bandwidth, signal power, and noise constrain the maximum achievable data rate. The discussion then moves from idealized theory to the realities of practical wireline links, including frequency-dependent channel loss, bandwidth limitations, equalization, modulation formats such as PAM-M, and the impact of noise and crosstalk. Through intuitive arguments and graphical explanations, the talk illustrates how modern high-speed links approach these theoretical limits and what techniques allow designers to continue pushing performance. The presentation aims to provide a clear conceptual framework for understanding the fundamental trade-offs between bandwidth, power, noise, and signaling complexity in wireline systems. It is intended for graduate students and practicing circuit designers, particularly those interested in high-speed I/O, SerDes architectures, and communication circuits. By connecting information theory to practical circuit design, the talk offers insight into both the limits of current copper-based links and the factors that may motivate future transitions to new interconnect technologies.Stochastic Search for Global Optimum - What happens when we stop fighting noise and let it compute
Abstract: If your day job involves taming noise, equalizing channels, and persuading electrons to behave at hundreds of gigabits per second, this talk offers a one-hour vacation from that world. No eye diagrams will be harmed; Instead, we will explore what happens when we deliberately embrace randomness, noise, and uncertainty, and ask whether they can be turned into a computational advantage. Think of this as intellectual cross-training for circuit designers. As CMOS scaling slows, performance gains increasingly come from architectural specialization rather than faster clocks. CPUs, GPUs, and DSPs provide steady but modest improvements, while truly dramatic speedups require hardware tailored to a broader class of problems. Optimization is one such class, quietly underpinning everything from logistics and finance to engineering design, medicine, and climate modeling. In this talk, we dive into digital annealing architectures that exploit massive parallelism and stochastic search to solve large optimization problems far faster than conventional simulated annealing. By implementing Markov Chain Monte Carlo techniques, including parallel tempering, directly in hardware, these systems can achieve speedups on the order of 1,000x to 10,000x for problems with thousands of variables. The aim is to show how hardware designers can think differently about performance when noise is no longer the enemy, but part of the solution, offering a glimpse of how CMOS can keep delivering surprises even as traditional scaling runs out of steam.
Biography: Yun-Shiang Shu (S’05–M’10–SM’19) received the B.S. and M.S. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 1997 and 1999, respectively, and the Ph.D. degree in Electrical and Computer Engineering from the University of California, San Diego, in 2008.
Since 2010, he has been with MediaTek Inc., Hsinchu, Taiwan, where he currently serves as Director of Technology. At MediaTek, he contributed to establishing analog-to-digital converter technology for 3G/4G mobile communications, which has become integral to the company’s mobile phone products. He now focuses on sensing technologies for SoC and IoT applications and has delivered MediaTek’s first biosensor product for consumer wearables.
Dr. Shu has published extensively on data-converter and analog front-end techniques, contributing to both industrial applications and academic research. Since 2013, he has served on the Technical Program Committee of ISSCC and/or the Symposium on VLSI Circuits. He is currently a Technical Program Committee member of the Symposium on VLSI Circuits, an Associate Editor of the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), and the Vice Chair of the IEEE SSCS Taipei Chapter.
Presentations:
Noise Shaping and Mismatch Error Shaping for SAR ADCs
Abstract: Over the last decade, SAR ADCs have become the dominant ADC architecture due to their energy and area efficiency. With continued process scaling, they can now achieve conversion rates of tens of MS/s with approximately 10-bit resolution. This increased data rate enables the use of oversampling to overcome their resolution limits through signal processing techniques, while maintaining sufficient signal bandwidth for a wide range of practical applications.
The resolution of SAR ADCs is fundamentally limited by comparator noise and nonlinearity arising from capacitor mismatch. By incorporating noise-shaping and mismatch error-shaping techniques, the noise and distortion within the signal bandwidth can be effectively suppressed, thereby enabling SAR ADCs to achieve higher resolution while preserving their energy- and area-efficient characteristics.
As noise-shaping SAR ADC designs have grown increasingly complex in recent years, this lecture will introduce the fundamental principles of noise shaping and mismatch error shaping for SAR ADCs in an intuitive manner.
Analog Front-End for Biosensors in Consumer Electronics
Abstract: Nowadays, biosensors for photoplethysmography (PPG) and electrocardiography (ECG) are widely deployed in consumer wearable devices, such as smartwatches and wristbands, to monitor users’ health conditions during sports, sleep, and daily activities. However, unlike biosignal acquisition in well-controlled medical settings, signal acquisition in consumer devices inevitably suffers from degraded signal quality due to poor sensor interfaces, motion artifacts, and environmental interference. These challenges impose demanding specifications on the analog front-end, despite tight constraints on sensor area, chip size, battery capacity, and overall device form factor.
This lecture will address these challenges and present circuit techniques that enable reliable PPG and ECG acquisition under highly variable conditions in consumer wearable devices.
Biography: Milin Zhang is an associate professor in the department of Electronic Engineering, Tsinghua University. She received her B.S. and M.S. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2004 and 2006, respectively, and her Ph.D. degree in the Electronic and Computer Engineering Department, Hong Kong University of Science and Technology (HKUST), Hong Kong. After finishing her doctoral studies, she worked as a postdoctoral researcher at the University of Pennsylvania (UPenn).
She joined Tsinghua University in 2016. Her research interests include designing of various non-traditional imaging sensors and biomedical sensing circuit, system design and applications. She was selected as an IEEE SSCS, IEEE CASS, IEEE WiE Distinguished Lecturer. She serves and has served as the AE of TCAS-II, TBioCAS, the AdCom member of SSCS, TPC member of ISSCC, CASS, CICC, A-SSCC and BioCAS, Chapter chair of the SSCS Beijing chapter.
Presentations:
Low Power Wireless Biopotential Sensor
Abstract: Biopotential signals acquisition plays a critical role in a human-computer interface system. Most of these biopotential signals distributed in the band of lower than kilo-hertz, or even lower than hundreds hertz. Precise acquisition of low amplitude signal at near DC frequency band is a challenge. In addition, the wearable/implantable scenario rises a high requirement in power efficiency, which causes a very limited power budget for the typically power hungry wireless data transmission. The existed commercial solutions, such as BLE and/or WiFi, are not suitable. This seminar introduces several System-on-Chip (SoC) key technologies for the wireless acquisition of the biopotential signals.
Electrochemical Electrodes and Readout Interface
Abstract: Electrochemical detection is widely used in medical diagnosis and health monitoring due to its real-time response and high accuracy. Both electrochemical electrodes and CMOS-based readout circuits have been continuously improved over the past decades. In terms of the readout circuit, either current-based or voltage-based circuits have been attempted. On one hand, the readout circuit of passive electrodes is developed towards the direction of high precision and high bandwidth. On the other hand, readout circuits for active electrodes are designed for multi-channel and adaptive non-ideality compensation. In the past decade, breakthroughs in ion-selective field effect transistor (ISFET) and organic electrochemical transistors (OECTs) have also enabled more precise electrochemical detection.
Terms through 30 April 2027
Presentations:
The Impact of Industry Trends on Wireline R&D
Abstract: Trends in high-performance computing and communication are creating new wireline connectivity demands. The increasing use of chiplets for AI computing and networking increases bandwidth demands in and out of the package and over die-to-die interfaces. Meanwhile, new paradigms for organizing computing within and between datacentres and across regional networks create new applications for optical data transmission. The resulting demands on the power, price and performance of transceiver circuits create new opportunities for innovation on high-performance analog front-ends, DSP, packaging, and optics.Talk Title #2: Scaling AI with Chiplet-Based Systems
Abstract: In the rapidly evolving landscape of artificial intelligence, chiplets are emerging as a transformative technology, paving the way for the next generation of AI systems. Chiplets permit the integration of more processing power within a single package, and allow for new connectivity solutions so that thousands of AI accelerators can work as a cohesive unit. Optical connectivity, facilitated by chiplets, offers high-speed data transmission with lower power consumption, crucial for handling the massive data loads in AI applications. The emerging chiplet ecosystem, underwritten by high-performance die-to-die interfaces, is throwing open the doors of innovation and facilitating the next wave of AI scaling.
Presentations:
AI-Enhanced RF/Mixed-Signal Circuits for Extreme Environments
Abstract: AI-driven design and optimization are transforming RF and mixed-signal circuits for extreme environments, such as high-radiation, cryogenic, and high-temperature conditions. This work explores reinforcement learning (RL) and generative models to enhance circuit robustness and adaptability. RL-based self-healing mechanisms leverage embedded sensors for real-time monitoring and dynamic recovery, while generative models accelerate design space exploration, enabling resilient and efficient circuit topologies. By integrating AI with adaptive hardware architectures, this approach enhances performance and reliability in harsh-environment applications.High-Speed Analog-to-Digital Data Converters
Abstract: High-speed analog-to-digital converters (ADCs) are critical for modern communication, computing, and sensing systems, demanding high-efficiency and fast conversion rates. This presentation explores advanced architectures, circuit techniques, and design optimizations to enhance ADC performance. Emphasis is placed on high-speed sampling, low-jitter clocking, and energy-efficient quantization techniques. Novel calibration and AI-enhanced methods further improve linearity and robustness, enabling next-generation high-speed data conversion for high-performance applications.Wireless Security for IoT Systems: RF Fingerprinting, Authentication, and Encryption
Abstract: As IoT systems become increasingly pervasive, ensuring secure wireless communication is critical to prevent unauthorized access and cyber threats. This presentation explores advanced techniques for wireless security, including RF fingerprinting for device identification, lightweight authentication protocols, and efficient encryption schemes tailored for resource-constrained IoT devices. By leveraging in-sensor machine learning, RF fingerprinting enhances security by uniquely identifying devices based on inherent hardware variations. Combined with robust authentication and encryption, these techniques strengthen IoT resilience against spoofing, eavesdropping, and other attacks, ensuring reliable and secure wireless connectivity.
Presentations:
Brain-Computer Interfaces: A Software-Hardware Co-Design Approach
Abstract: Brain-Computer Interfaces (BCIs) are technologies that communicate directly with the brain, and can improve the quality of life of millions of people with brain circuit disorders. Motor BCIs are among the most powerful examples of BCI technology, where microelectrode arrays are implanted into motor regions of tetraplegic participants. Movement intentions are decoded from recorded neural signals into command signals to control a computer cursor or a robotic limb. However, these systems fail to deliver the precision, speed, degrees of freedom and robustness of control enjoyed by motor-intact individuals. To enhance the overall performance of the BCI systems and to extend the lifetime of the implants, newer approaches for recovering functional information of the brain are necessary. To infer intent, BCI must extract features that accurately estimate neural activity. However, the degradation of signal quality over time hinders the use of standard techniques. In this presentation, we show that a convolutional neural network can be used to map electrical signals to neural features by jointly optimizing feature extraction and decoding under the constraint that all the electrodes must use the same neural-network parameters. In all human participants, our proposed neural network led to significant offline and online performance improvements in a cursor-control task across all metrics, outperforming the rate of threshold crossings and wavelet decomposition of the broadband neural data (among other feature-extraction techniques). We will show that the trained neural network can be used without modification for new datasets, brain areas and participants. We will also discuss software-hardware co-design approaches for energy-efficient hardware implementation of learning-based BCI systems towards miniaturized implantable and wearable devices.Electronic-Photonic Co-Design for High-Speed Data Communication and Beyond
Abstract: Data centers continue to demand interconnect solutions with higher bandwidth densities and improved energy efficiency. Furthermore, applications such as chip-to-chip interconnects in switches, high-performance FPGAs and GPUs call for compact form-factors, high-volume production and low-cost. Silicon Photonics (SiP)-based transceivers, when co-packaged with CMOS electronics, offer a promising avenue to meet these demands with speeds exceeding 100 Gb/s per wavelength. In this talk we focus on architectural and circuit-level techniques for both PICs and EICs to improve the energy-efficiency at high data rates. We will discuss how various types of optical modulators and optical architectures can be employed to achieve higher-order modulation schemes. We will first present a 100Gb/s 3D integrated Sip-CMOS PAM4 optical transmitter system. The photonic chip includes a push-pull segmented MZM structure using highly capacitive, yet optically efficient MOSCAP phase modulators. Co-design and optimum bandwidth enhancement techniques are employed to achieve high data rates and energy efficiency. Next a 100Gb/s DAC-less PAM-4 transmitter and a 200Gb/s QAM-16 transmitter in a multi-micron silicon photonics platform using binary-driven SiGe EAMs will be presented. In the second part of this talk, we will briefly show another example of co-designed electronics and photonics for sensing applications. We present a fully integrated fluorescence (FL) sensor in 65nm standard CMOS comprising on-chip bandpass optical filters, photodiodes (PDs), and processing circuitry. The metal/dielectric layers in CMOS are employed to implement low-loss cavity-type optical filters achieving a bandpass response at 600nm to 700nm range suitable to work with fluorescent proteins (FPs), which are the widely used bio-reporters for biomedical and environmental sensing.Wireless Medical Devices for Sensing and Navigation
Abstract: Microscale implantable and wearable devices will transform the field of medicine in the near future. This talk will focus on design and implementation of miniaturized minimally invasive devices for continuous monitoring and closed-loop therapeutic systems. In the first part of this talk, an MRI-inspired approach for precise localization and tracking of small tags, smart pills and sensors inside the body will be presented. The prototype devices called ATOMS (Addressable Transmitters Operated as Magnetic Spins) are designed to behave similar to real atoms in the body without the need for the strong magnetic field of MRI. We will also show how these devices can be used for 3D navigation during high-precision surgeries. As part of this work, we will present a novel 3-D magnetic sensor in CMOS with high-resolution and ultralow-power operation. The sensor was successfully used for 3-D localization and tracking of catheters with 500-µm mean accuracy in a surgical operation room. In the second part of this talk, we will discuss miniaturized multi-modal wearable and implantable biosensors. In particular we will focus on energy harvesting techniques for such applications. I addition to wireless RF energy harvesting, a biofuel-cell-based energy harvester with 86% peak efficiency and 0.25V minimum input voltage using source-adaptive MPPT will be presented.
Presentations:
Who will design tomorrow’s analog integrated circuits: humans or AI-based synthesis?
Abstract: Analog/mixed-signal integrated circuits are key in applications where electronics interface with the physical world. The design of analog circuits, however, is time consuming and prone to errors, often requiring multiple redesign cycles. The rebirth of AI and machine learning, and the recent rise of generative AI methods, on the other hand, create a whole new spectrum of techniques to automate this process. This invited talk will explore the high potential of using advanced machine learning (ML) techniques to automatically synthesize and lay out analog integrated circuits. What is hype and what will be feasible? Will we still need analog designers in the future and how will they operate?Designing analog functions without analog circuits
Abstract: The continuous progress of CMOS semiconductor technology fuels the ongoing digitization in our daily life. Yet, analog/mixed-signal integrated circuits are key in applications where electronics interface with the physical world. This presentation focuses on core challenges in the design of such analog interfaces, where low cost, low power consumption and high reliability are major targets besides raw performance. Key to achieving solutions with small area (cost) and low power is to design the analog functions in a highly digital manner, i.e. without actual analog circuits. This will be illustrated with several practical design examples for sensor interface readout and data conversion circuits for applications such as automotive and biomedical.
Presentations:
Emerging Chip-Scale Terahertz Systems for Sensing, Metrology and Security Applications
Abstract: Terahertz (THz) electronics is attracting increasing attentions due to the recent “beyond-5G” research. On the other hand, it may surprise many that devices for THz wave generation and detection had in fact been reported as early as one century ago, and even the CMOS-based low-cost THz circuit also already has more than 15 years of history. Despite those advances, exploration of unique and practical applications of the THz technology, especially the applications for THz chip-scale systems, is still far from enough. In this talk, we introduce some recent research outcomes in this regard. Showcased prototypes include high-angular-resolution radars, ultra-miniaturized and unclonable RFIDs, molecular spectrometer-based gas sensors and clocks, low-heat-load cryogenic interconnects, among others.Chip-Scale Wave-Matter Interactions at RF-to-Light Frequencies: Circuits, Systems and Applications
Abstract: Traditional EM spectral sensors using integrated circuit technologies (e.g. automotive radars, security imagers, cameras, etc.) are normally based on wave scattering or absorption by macroscopic objects at remote distance; the operations are also not specific in wave frequencies. In the past couple of years, a new paradigm of chip-scale EM spectral sensing emerges with features complementary to the above: they utilize various modalities of interactions between EM waves with high-precision frequency control and microscopic particles (molecules, atoms, etc.) in close proximity to the chip. This progress is enabled by the recent advances of silicon devices and processes, especially the increase of circuit operation frequencies into the terahertz regime. Chip-scale sensing and metrology systems with new capabilities, higher performance and unprecedented affordability now become possible. Examples include THz gas spectroscopy sensors, on-chip “atomic-clock-grade” frequency references, room-temperature CMOS-quantum magnetometers, etc. This talk will present the basic physics of a few types of wave-matter interactions, key enabling technologies, as well as the designs and prototypes of chip systems. We will also discuss their potential applications in bio-chemical analysis, wireless networks, PNT (positioning, navigation & timing), security and so on.
Presentations:
Energy-Efficient and Fully Integrated Frequency References: Overcoming Stability and Accuracy Challenges
Abstract: Reliable frequency references are essential for various applications, from precise timekeeping in calendar functions to stable clocks for radios and microcontrollers. While quartz crystal-based references deliver excellent performance, their bulk and incompatibility with monolithic integration limit their scalability. In this talk, I will explore techniques for realizing fully integrated frequency references that are both energy-efficient and highly stable across temperature, voltage, and process variations. I will discuss advanced methods to enhance the frequency accuracy of RC oscillators through precise cancellation of resistor temperature coefficient across PVT variations. Additionally, I will examine the long-term impact of component aging on frequency stability and present practical strategies to mitigate its effects.
Presentations:
ADC Enhancement Techniques in Advanced CMOS Technologies
Abstract:The aim of this presentation is to introduce the basics and various practical illustrations of advanced ADC enhancement techniques in a nutshell. With applications pushing for higher resolutions & data-rates, and technology-scaling favoring digital design, the use of digital techniques to enhance ADC performance is inevitable. This talk will first summarize trends and trade-offs regarding the use of these digital-intensive techniques before illustrating some popular and recent examples from literature, including calibration and enhancement techniques as well as digitally-inspired analog circuit design. Besides that, an outlook is given regarding future challenges and opportunities in advanced CMOS technologies.Energy Efficient ADC Design Techniques
Abstract:In this review presentation, we will have a look at ADC efficiency trends over the years as function of ADC architecture, resolution, and sampling rate. After that, state-of-the-art design examples from literature are reviewed, and the key techniques to achieve high efficiency are highlighted. This includes techniques at circuit, system, layout and algorithmic levels. ADC architectures such as Pipelined, Sigma-Delta, SAR, Noise-Shaping SAR, and others are all briefly covered. The presentation concludes with a reflection on the differences and similarities of the highlighted efficiency features.ADC Innovations for Improved Resolution, Power and Form Factor
Abstract:ADC design is progressing rapidly over time thanks to innovations in architecture, circuit implementation, and technology scaling. For many emerging applications, for instance in the field of IoT or medical devices, converters with high resolution, low power consumption, and a small form factor are desired. In this tutorial-level presentation, we will explain the general trade-offs for these performance metrics, and we will highlight some of the recent developments that pushed the state-of-the-art forward. The talk will also give some insight into the challenges when embedding converters in an overall system.Ultra low power SAR ADCs and versatile, dynamic sensor interfaces
Abstract:In this talk, we will take a look at ultra low power sensor interfaces for IoT applications. In such applications, the sensing operation is often done at a relatively low frequency, and sometimes it is heavily duty-cycled, or it should be triggered by particular events or thresholds. For that reason, dynamic operation is beneficial as compared to static operation. We will review ADC and sensor interface architectures that can operate dynamically and that can be triggered by a single clock pulse. Various capacitive and resistive sensor interfaces are shown, and the final example shows a resistive-based temperature sensor interface including analog correction techniques for gain, offset and distortion.
Presentation(s):
Systematic Equation-Based Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW
Abstract: As data converters find their way into virtually every microelectronic device, developers of application-specific systems-on-a-chip increasingly suffer from large development costs arising from limited specialized design expertise and the tedious process of migration to new technology nodes. In this talk, we introduce three pieces of analysis for the optimum design of key building blocks in the ADC: a) Distortion and bandwidth of a passive sample and hold (S/H) circuit, b) noise and offset of a regenerative comparator, and c) jitter analysis for a clock distribution path. By deploying these analysis tools, a systematic design framework of ADCs is demonstrated with the optimized design of a self-timed charge-redistribution SAR ADC.Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
Presentations:
Capacitance-to-Digital Converters (CDCs), Interfacing with Capacitive Sensors
Abstract: Capacitive sensors are extensively utilized for IoT applications due to their low noise and temperature dependence. They find can be used to sense a broad range of physical quantities, such as pressure, humidity, acceleration, gas molecules, and proximity. To read out such sensors and extract useful information, high performance capacitance-to-digital converters (CDCs) are required. Their design is challenging due to the many design tradeoffs that must be made between performance parameters such as energy efficiency, sensing resolution, and input range. In this talk, the basic principles of capacitive sensors, the design goals and tradeoffs of CDCs, and conventional circuit structures will first be reviewed. Then, more recent and advanced circuit structures and design techniques to improve energy efficiency, sensing resolution, and input range will be presented. Lastly, some future research directions in the design and application of CDCs will be discussed.Process-Scalable Low-Power Amplifiers
Abstract: Dynamic amplifiers have received increasing interest in state-of-the-art systems due to their superior power efficiency and scalability with technology. They have, for example, found many applications in low-power ADCs as error/residue amplifiers or loop filters. This talk will introduce various types of dynamic and ring amplifiers. Their conventional structures and basic operational principles will be explained, and a diverse range of topologies, as well as corresponding design tradeoffs, will be described. The effects of PVT variations on their performance and design considerations will also be discussed. Through this tutorial, attendees will obtain a solid understanding of the basics of dynamic and ring amplifiers, including design choices, tradeoffs, and considerations, along with an overview of recent developments.Low-Power Bioimpedance Measurement Techniques for Sensing and Imaging
Abstract: Bioimpedance measurement is one of key methods to interface with biology and finds a very wide range of sensing and imaging applications, including body composition analysis, cardiovascular monitoring, respiratory monitoring, detection of tissue abnormalities, characterization of tumor progression, neural activity monitoring, and functional localization of peripheral nerves. In this talk, the basic principles of bioimpedance measurement and the overall circuit system structure composed of an excitation signal generation circuit block and an impedance readout circuit block will be reviewed first. Then, the design goals, challenges, and tradeoffs of such circuit blocks and integrated systems will be explained. Also, various design techniques that have been proposed to improve diverse performance parameters, such as energy efficiency, measurement accuracy, resolution, dynamic range, frequency coverage, and throughput, will be introduced and discussed with the foremost focus on the low-power design aspect, which is essential for battery-powered or battery-less systems.Building Neural Interfaces: Key Components, System Integration, and Technical Hurdles
Abstract: Implantable neural interface systems are widely used for neurotherapeutics to treat neurological disorders and neuroprosthetics to restore neurologically impaired body functions. In this talk, after introducing a generic structure of fully implantable neural interface systems, we investigate how this structure is varied when used for different applications. Then, the challenges faced in developing key components of the system, such as neural recording and stimulation, wireless power transfer, wireless data communication, and signal processing, are explained, followed by the discussion of system integration challenges. Lastly, recently reported neural interface system examples are introduced to showcase how researchers are trying to address those challenges.
Presentations:
Circuit Labs at the Lunch Table with MOSbius
Abstract: Learning integrated circuit design requires gaining a broad range of skills and knowledge including circuit analysis and design, signals & systems, applied electro-magnetics, and semiconductor physics. Learning theory has always been most accessible through books or now the internet. Simulation tools are now also widely available on personal computers, including open-source versions. But, learning measurements so far has been mostly confined to school or industry laboratories. Yet, physical intuition and practical experience keeps playing a significant role in the development of successful, high performance integrated circuits. We will present the MOSbius platform that allows a student or designer to experiment with IC-style, analog, CMOS circuits at the lunch table. This unique platform uses a custom chip with CMOS building blocks that can be wired on a breadboard or with a programmable on-chip switch matrix. Measurements can be conducted using an affordable, all-in-one, USB lab instrument. Ready-to-go experiments are provided to learners and instructors on https://mosbius.org. Nothing can substitute for the aha moment when you observe a circuit finally working. The debugging process to bring-up the circuit teaches the designer essential lessons that carry over to high performance circuits in highly scaled technologies. The MOSbius platform aims to make lab experience widely accessible and affordable to learners.Teaching IC Design: From Concepts to Testing a Fabricated Custom Chip
Abstract: In this talk I will share my experience of developing the VLSI Design Lab (https://vlsidesignlab.org) at Columbia University, a class where students define an integrated circuit; design, simulate, and lay it out; have the chip fabricated; and test and demonstrate their chip in an application. The lab offers a holistic experience not only of the chip design process, but also of integrating the chip in an application. It exposes students to many topics that are often overlooked in lecture or simulation-based courses. The lab has been taught six times and more than 55 chips have been taped out by more than 140 students. Popular designs include class-D audio amplifiers, PPG-based monitors, digital clocks, or ultrasound transceivers; we have also built a RISC-V processor, neural processing units, an FPGA, ADCs and RF circuits. I will discuss the unique educational benefits that students gain from this type of course. Whereas the logistics of offering a lab like this might look daunting, there are many tools and services available that along with careful organization and scheduling make it possible.
Presentation:
High-performance Energy-efficient Compute-in-Memory and AI accelerators for sub-18A Technologies
Abstract: This presentation will highlight some of the emerging challenges and opportunities for sub-18A process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-18A technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for digital and analog in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
Presentations:
The Road to Gate-All-Around CMOS
Impact of Advanced CMOS Technology on Analog Design
Truths, Lies, and Simulations - A Tutorial on Process Corner Models
Presentations:
Precision CMOS Amplifiers
Abstract: In CMOS, mismatch is a fact of life! In amplifiers, it causes offset voltages of a few millivolts and gain error of a few percent. However, amplifier performance can be dramatically improved by the application of dynamic techniques such as auto-zeroing, chopping and dynamic element matching. Offset can be reduced to the microvolt level and gain errors less than 0.1% can be achieved in standard CMOS. Compared to the alternatives, i.e. the use of huge devices or trimming, the use of dynamic techniques has the added advantage of also reducing 1/f noise and drift, making it possible to design amplifiers that are thermal-noise limited. In this tutorial, an introduction to auto-zeroing, chopping and dynamic element matching will be given, their pros and cons highlighted and recent advances in the state-of-the-art reviewed.Smart Sensors in Standard CMOS
Abstract: Sensors are everywhere! Temperature sensors throttle SoCs, accelerometers activate airbags, and gyroscopes and magnetometers are now standard smart phone components. These are all examples of smart sensors, i.e. sensors that are co-integrated with their readout electronics and so provide digital output. However, processing the weak analog output of typical sensors is quite challenging, especially when it must be done in standard CMOS, whose precision is limited by 1/f noise, component tolerances and mismatch. In this tutorial, a system approach to the design of smart sensors will be presented. The use of dynamic techniques, such as chopping, auto-zeroing, dynamic element matching and sigma-delta modulation, to trade speed for precision will be discussed. The proposed methodology will be illustrated by case studies describing the design of state-of-the-art CMOS sensors for the measurement of wind velocity, magnetic field and temperature.The Zoom ADC: An Evolving Architecture
Abstract: Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (ΔΣM) to efficiently achieve high resolution and dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This talk presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 μm technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only a few hundreds of μWs.Giving Great Technical Talks
Abstract: Technical ideas only become impactful if they are effectively communicated. The bad news is that most engineers are not natural communicators. The good news, though, is that most of them can learn how to become good communicators. In this talk, I will share a few guidelines to better presentations, based on over 20 years of successfully helping my students and colleagues to give great technical talks.Precision Band-Gap Circuits: Less is More!
Abstract: The ubiquitous bandgap voltage reference is used in nearly every integrated circuit manufactured today. It also forms the heart of most integrated temperature sensors. Despite decades of use, however, recent research has shown that it is still possible to improve on the state-of-the-art by adhering to the old adage: less is more! By following this approach, voltage references and temperature sensors have been realized with relative inaccuracies as low as 0.15% over the military temperature range (-55C to 125C).
Presentations:
Talks may be presented in English or Spanish.Circuits and Technology Advancements for Resiliency and Reliability
Abstract: Next-generation SoCs for the Zetta-Scale computing era will be developed with increased integration of our compute, memory and communication systems in optimized advanced packaging solutions. The complexity of these systems is growing exponentially and the need to increase reliability while achieving high energy-efficiency is paramount. We will explore the challenges and opportunities in technology, packaging and circuits to enable resilient and reliable circuits and systems. We will study several cases of advanced circuit design to address those growing challenges.The Awesome World Enabled by Semiconductors (INSPIRE Program)
Abstract: Semiconductors are pervasive in all aspects of society. We will explore the technological advancements that have led to the explosion of semiconductors in our world and look at different circuit applications that showcase that impact. We will also learn how the Solid-State Industry and our Society has shaped our field and the opportunities that we have to develop and grow the next generation of engineers.SSCS also maintains an Agreement of Cooperation with the IEEE Microwave Theory and Technology Society (MTT-S.) Their list of Distinguished Microwave Lecturers is available here.