What's New
SSCS Chapter Awards
The following Chapter Awards are presented annually to chapters that meet and exceed the parameters listed below. The awards are based on a calendar year (January-December) and are presented during ISSCC.
One Chapter PER award will be granted each year, although, the Chapters Steering Committee may recommend two awards in an exceptional year or forgo the presentation of any of the awards if no qualified cancidates are avaliable. The Chapters Steering Committee reviews and rank-orders all nominations based on the criteria listed below.
Apply here! Deadline for applications is Wednesday, December 7, 2022
Feature Article
Please join us for the inaugural Solid-State Circuits Society (SSCS) Open Journal Webinar Series. This series will feature two talks on two papers from SSCS open journals: IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) and IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC).
Design Techniques for High-Speed Wireline Transmitters
Presented by Behzad Razavi
Wednesday, December 7, 2022 at 11:00 AM EST
IGZO CIM: Enabling in-memory computations using multi-level capacitorless Indium Gallium Zinc Oxide based embedded DRAM technology
Presented by Jaydeep P. Kulkarni and Siddhartha Raman
Tuesday, December 13, 2022 at 10:00 AM EST
Technology Spotlight
SSCS December Technical Webinar
Digital Beamforming with Bandpass ADCs and Bitstream Processing
Virtual Webinar presented by Michael Flynn
Join us on Wednesday, December 14th at 9:00 AM EST.
Multi-antenna systems and beamforming play a critical role in mm-wave communication by counteracting path loss. In addition, spatial filtering and multiplexing further increase channel capacity. Moreover, large arrays are desirable, as an arrayed system's SNR and spatial selectivity improve with more extensive array size. In addition, digital arrays offer better flexibility, reconfigurability, and beam accuracy and enable efficient multi-beam generation.
Bitstream processing (BSP) is an emerging technique for power and area-efficient digital beamforming. An array of bandpass continuous-time ADCs digitizes high IF signals, relaxing anti-alias requirements and eliminating the need for analog IQ down conversion. BSP directly operates on the undecimated ADC quantizer outputs to reduce the power consumption and die area of digital processing. We demonstrate the potential of this approach in a single-chip 16-element digital beamformer. We also show that BSP can facilitate both true-time-delay and phased array beamforming.
