Jun Deguchi received the B.E. and M.E. degrees in machine intelligence and systems engineering and the Ph.D. degree in bioengineering and robotics from Tohoku University, Sendai, Japan, in 2001, 2003, and 2006, respectively. In 2004, he was a Visiting Scholar at the University of California, Santa Cruz, CA, USA. In 2006, he joined Toshiba Corporation, and was involved in  design of analog/RF circuits for wireless communications, CMOS image sensors, high-speed I/O, and accelerators for deep learning. From 2014 to 2015, he was a Visiting Scientist at the MIT Media Lab, Cambridge, MA, USA, and was involved in research on brain/neuro science. In 2017, he moved to Kioxia Corporation, and has been a Research Lead of an advanced circuit design team working on high-speed I/O and deep learning/in-memory accelerators. Dr. Deguchi has served as a member of the international technical program committee (TPC) of IEEE International Solid-State Circuits Conference (ISSCC) since 2016, and IEEE Asian Solid-State Circuits Conference (A-SSCC) since 2017. He has also served as a TPC vice-chair of IEEE A-SSCC 2019, a Far-East (FE) secretary for IEEE ISSCC 2021, and a review committee member of IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2020. He is serving as a FE vice-chair for IEEE ISSCC 2022.

Dina El-Damak received B.Sc., and M.Sc. degrees from Ain Shams University, Egypt in 2007, and 2010, respectively. She received the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 2012 and 2015, respectively. From 2016 to 2020, she was an assistant professor at the University of Southern California. She is currently an assistant professor at the University of Science and Technology at Zewail City, Egypt, where she focuses on the design of CMOS image sensors, solar irradiance forecasting, energy harvesting, power management circuits, and hardware for machine learning applications. She is a senior member of IEEE. Additionally, she has been a member of the Technical Program Committee of the IEEE Custom Integrated Circuits Conference and the Women in Circuits Committee since 2019. She has been a member of the ISSCC Student Research Preview (SRP) committee since May 2020, and the co-chair of the poster session at the ISSCC 2021 SRP. She is the co-chair of the Power Management Subcommittee of IEEE CICC 2020 and 2021.

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge in 1996 and 1997, respectively. She joined Motorola in Tempe, AZ in 1997 and worked in the area of RF circuit design.  In 2003, she joined Texas Instruments in Dallas, Texas and is a Fellow in the Connectivity business unit.  She develops circuits and techniques for reducing cost, power consumption, and circuit board area for low power wireless connectivity products.  Her current focus areas are architectures for efficient wireless systems, low power oscillators and MEMS circuitry.  She has published >50 papers, most of them in IEEE journals or conferences.   She has written a book chapter titled “Synchronization Clocks for Ultra-Low Power Wireless Networks” which was published by Springer as a part of the book “Ultra-Low-Power Short-Range Radios”.  Danielle holds 19 issued US patents and has given multiple university and IEEE conference tutorial and workshop sessions.  She was a member of the Technical Program Committees for the IEEE RFIC Symposium for conferences years 2014 and 2015, the IEEE International Solid-State Circuits Conference for conference years 2015-2019, and the VLSI Symposium starting in 2019.   She is actively involved in initiatives within Texas Instruments to increase diversity in senior technical roles. 

Chulwoo Kim received the B.S. and M.S. degrees in electronics engineering from the Korea University in 1994 and 1996, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 2001.

In 1999, he worked as a summer intern at the Design Technology at Intel Corporation, Santa Clara, CA. In May 2001, he joined IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September 2002, he has been with the School of Electrical Engineering, Korea University, where he is currently a Professor. He was a Visiting Professor at the University of California at Los Angeles in 2008 and at the University of California at Santa Cruz in 2012. He is a coauthor of two books, namely, CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 4th edition 2014) and High-Bandwidth Memory Interface (Springer, 2013). His current research interests are in the areas of wireline transceiver, memory, power management and data converters.

Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award (1996), the ISLPED Low-Power Design Contest Award (2001, 2014), the DAC Student Design Contest Award (2002), SRC Inventor Recognition Awards (2002), the Young Scientist Award from the Ministry of Science and Technology of Korea (2003), the Seoktop Award for excellence in teaching (2006, 2011) and ASP-DAC Best Design Award (2008) and Special Feature Award (2014), Korea Semiconductor Design Contest: Prime Minister Award (2016). He served on the Technical Program Committee of the IEEE International Solid-State Circuits Conference and as a Guest Editor for IEEE Journal of Solid-State Circuits. He is currently on the editorial board of IEEE Transactions on VLSI Systems and the Chair of the SSCS Seoul Chapter. He has been elected as Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2015–2016.

Aravind Tharayil Narayanan (Senior Member, IEEE) received the B.Tech. degree in electronics and communication engineering from Calicut University, India, in 2003, the M.S. degree in very large scale integration (VLSI)-CAD from Manipal University, Manipal, India, in 2009, and the Ph.D. degree from the Tokyo Institute of Technology, Tokyo, Japan, in 2016.,He is currently a Researcher with Ericsson AB, Lund, Sweden. His research interests include data converters, frequency generation and recovery, high-purity oscillator design, and mixed-signal design.

He has been the receiver of prestigious Monbukagakusho Scholarship from Japanese Government in 2011. He has authored and co-authored more than 25 conference papers, out of which, more than 20 are IEEE conferences including ISSCC, ESSCIRC, ASSCC, etc., and 10 journal papers, out of which 7 are IEEE titles including JSSC (invited from ESSCIRC 2015).  He served as the chair of IEEE branch at Tokyo Institute of Technology from 2014-2015 and he has also been serving IEEE as a reviewer for titles such as IEEE JSSC, T-VLSI, SSCL, TCAS-I and TCAS-II.

Yusuke Oike received the B.E., M.E., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2000, 2002 and 2005, respectively. In 2005, he joined Sony Corporation, Tokyo, Japan, where he was involved in research and development of architectures, circuits, and devices for image sensors. From 2010 to 2011, he was a visiting scholar at Stanford University, CA. Currently, he is in charge of research and development of CMOS image sensors as Deputy Senior General Manager of Sony Semiconductor Solutions, Japan. He is appointed as Distinguished Engineer of Sony Corporation. He is also a director of Sony Advanced Visual Sensing AG at Zurich. His current research interests include pixel architecture, mixed-signal circuit design for image sensors, and image processing algorithms.

He has published more than 50 technical publications, including 8 ISSCC, 5 VLSI Symposium, and 3 IEDM papers. He has given several invited talks, including ISSCC Forum in 2018 and 2021, and IEDM Tutorial in 2020. He is a senior member of IEEE. He has served technical program committees of international conferences, including ISSCC IMMD sub-committee member for ISSCC 2012-2016, VLSI Circuits Symposium committee member for VLSI 2016-2019, and VLSI Circuits Symposium Program Chair for VLSI 2020 and 2021.

Frank Omahony leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Senior Principal Engineer. His team coordinates circuit-process co-design for wireline I/O at Intel. They also design and test the first I/Os on each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab. His past work includes high-speed and low-power transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank has been on the ISSCC Technical Program Committee since 2012 including five years as the Wireline Subcommittee chair. He currently serves as the ISSCC Forums Chair. Since 2003 he has published over 40 papers in peer-reviewed conferences and journals on the topic of wireline transceivers and clocking. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. He is a Senior Member of the IEEE and served as an IEEE Distinguished Lecturer.

Farhana Sheikh (IEEE SM’14, IEEE M’93) received the B.Eng. degree in Systems and Computer Engineering with high distinction and Chancellor’s Medal from Carleton University, Ottawa, Canada, in 1993 and the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1996 and 2008, respectively. From 1993 to 1994 she worked at Nortel Networks as a software engineer in firmware and embedded system design. From 1996 to 2001, she was at Cadabra Design Automation as software engineer and senior manager.  She joined Intel Labs in 2008 after her PhD and worked in various roles as a senior researcher and manager in the area of digital circuits for cryptography, graphics, and next generation wireless systems.  Since November 2018, Farhana has been working as a Senior Staff Scientist in Intel’s Programmable Solutions Group Technology Innovation and Strategy Office where she leads multiple USG research programs for Intel.  Her research focuses on 2D and 3D multi-die heterogeneous integration, mm-Wave and THz distributed/non-distributive massive MIMO circuits and architectures, high-frequency wireless control for quantum computers, adaptive and intelligence-based circuits/architectures for next generation secure wireless systems, and cryogenic CMOS circuits. She has published 48 papers and filed 22 patents in the field of solid-state circuits and is the co-recipient of two prestigious ISSCC Lewis Award for Outstanding Paper for work published at ISSCC 2012 and ISSCC 2019.  In 2021 Farhana was a co-recipient of the ISSCC 2020 Jan Van Vessem Award for Outstanding European Paper.  She has also received the 2020 ISSCC Evening Session Award and the 2019 ISSCC Demonstration Session Certificate of Recognition. Farhana has demonstrated strong technical leadership by initiating research and development in new emerging technology areas, and by building strong, diverse technical teams to deliver on-time innovative and high-quality solutions to difficult problems as per corporate or academic objectives.  She has technically mentored and led multiple intern projects at Intel, and university-industry collaborative research projects and programs.  Numerous publications, patents, and awards are a testament to her imaginability and research ability to solve new and difficult engineering problems.  Farhana is the IEEE Solid-State Circuits Society (SSCS) Oregon Chapter Chair, an IEEE Senior Member, and holds technical program committee and co-chair positions in multiple solid-state circuits (VLSI Symposium, ESSCIRC/ESSDERC, CICC) and signal processing conferences (TPC Co-Chair SiPS 2020 and SiPS 2021).  Farhana chaired and co-organized the first SSCS Women in Circuits “Rising Stars” Workshop at ISSCC 2020.