SSCS AdCom Election and Petition Processes
2019 SSCS AdCom Election for term 2020-2022
Each year, the IEEE Solid-State Circuits Society (SSCS) rotates out the five Member-at-Larges whose term on the AdCom will be ending in December. This is done through the annual SSCS AdCom Election, which is organized by the SSCS Nominations Committee and Chaired by the current SSCS Past President. In 2019, the Chair is Jan Van der Spiegel and the election term is 2020-2022.
The 2020-2022 SSCS AdCom Member-at-Large Election is now OPEN. If you are eligible to vote, you should have received an email with election information. Voting can be done online: https://eballot4.votenet.com/IEEE. Voting will close on October 24th at 4:00 PM ET.
2019 SSCS AdCom Nominations Slate (TERM 2020-2021)
Alvin Loke (S’89–M’99–SM’04) is an industry veteran working on CMOS technology and design since 1998, and has been an active volunteer with the IEEE Solid-State Circuits Society since 2003. He received the B.A.Sc. degree in engineering physics with highest honors from the University of British Columbia, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University. He was recipient of a Canadian NSERC 1967 Scholarship and has interned at Sumitomo Electric Industries, Texas Instruments, and Motorola. Upon graduation, he worked several years in CMOS process integration at HP Labs and Chartered Semiconductor (as an Agilent assignee) before shifting to wireline design and design/technology interface at Agilent, Advanced Micro Devices, and Qualcomm. Alvin is presently a Director in the TSMC San Diego Design Center working on next-generation CMOS analog/mixed-signal design and technology co-optimization. He has authored over 50 publications (including a CICC 2018 Best Paper and many invited presentations) and holds 25 US patents. Alvin is currently the IEEE Solid-State Circuits Society (SSCS) Webinar Coordinator for North America, Chair of the San Diego SSCS Chapter, and VLSI Symposia committee member. In the past, he has served as a CICC 2006-2012 committee member, SSCS Fort Collins Chapter officer (2003-2013), SSCS Chapters committee member, IEEE Journal of Solid-State Circuits (JSSC) and IEEE Solid-State Circuits Letters (SSCL) guest editor, inaugural SSCS Webinar Taskforce Chair, and SSCS Distinguished Lecturer (2012-2013). The SSCS Fort Collins chapter he led was awarded the SSCS Outstanding Chapter Award in 2005 and Denver Section Chapter of the Year three times. He also received the IEEE Region 5 Outstanding Member Service Award in 2010.
Seng-Pan U (Ben) received the dual Ph.D. (Hons.) degrees from the University of Macau (UM) and the Instituto Superior Técnico (IST), Portugal in 2002 and 2004 respectively. He is one of the pioneers and leaders with transformational impact and contributions on the development of the SSC design research activities in both academia and industry in Macau. Currently, he is Deputy Director of State-Key Laboratory of Analog & Mixed-Signal VLSI, Visiting Professor of FST of UM. He is also the co-founder, corporate R&D Director, and Site General Manager of Synopsys Macau Ltd (Former Chipidea Microelectronics Macau). He is also the appointed member of the S&T Commission of China Ministry of Education and Macau S&T committee. He is currently IEEE Fellow (elevated by SSCS). He founded the SSCS Macau chapter, and as the Chairman received the 2012 SSCS Outstanding Chapter Award. He was a member of the SSCS Fellow Evaluation Committee (2016-18). He was an IEEE SSCS Distinguished Lecturer (2014-15) and A-SSCC 2013, ISSCC 2018, and ISCAS 2018 Tutorial Speaker. He was ISSCC ITPC and China country representative (2014-18), and has successfully led the influential regional promotion and press conference, and contributed to the ISSCC plenary and forum. He was also the A-SSCC subcommittee Chair (2016-18), and the Organization Chair of A-SSCC 2019 in Macau. He co-authored 200+ publications, 5 books, and co-holds 13 US patents. He is the co-recipient of the ISSCC Takuo Sugano Award (2017) and ESSCIRC Best paper award (2014), and he is the advisor for 30+ student awards, including SSCS Pre-Doctoral Achievement Award, ISSCC Silk-Road Award, A-SSCC Student Design Contest, and more. He was also elected as the “Scientific Chinese of the Year 2012,”. He received the HLHL S&T Innovation Award (2010), National S&T Progress Award (2011), 8 Biennale Macau S&T Award (2012-18), and Research Achievement Gold Award and Enterprise Innovation Award in the first Business Award of Macau (2013). In recognition of his contribution in academic research & industrial development, he was awarded by Macau SAR government the Honorary Title of Value in 2010.
Hoi-Jun Yoo is an ICT Chair professor at the School of Electrical Engineering and the director of the System Design Innovation and Application Research Center (SDIA) at Korea Advanced Institute of Science and Technology (KAIST). He was the TPC Chair of the ISSCC 2015, a Plenary Speaker of the ISSCC 2019 with a talk entitled “Intelligence on Silicon: From Deep Neural Network Accelerators to Brain-Mimicking AI-SoCs”, the Chair of Technology Direction (TD) subcommittee of the ISSCC 2013. He is an IEEE fellow (since 2008), an Executive Committee member of the Symposium on VLSI, and a Steering Committee member of the A-SSCC, of which he was nominated as the Steering Committee Chair from 2020 to 2025. He was the VCSEL pioneer in Bell Communications Research at Red Bank, NJ,USA, and the manager of the DRAM design group at Hyundai Electronics during the era of 1M DRAM up to 256M SDRAM. From 2003 to 2005, he served as the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interest includes Bio-Inspired Artificial Intelligence (AI) chip design, Multicore AI SoC design including DNN accelerators, Wearable Healthcare Systems, Network-On-Chip, and High-Speed Low-Power Memory. He has published more than 400 papers, and wrote or edited 5 books: “DRAM Design” (1997, Hongneung), “High Performance DRAM” (1999 Hongneung), “Low Power NoC for High Performance SoC Design” (2008, CRC), “Mobile 3D Graphics SoC” (2010, Wiley), and “Bio-Medical CMOS ICs” (Co-edited with Chris Van Hoof, 2010, Springer), and co-written chapters in numerous books. Dr. Yoo received the Order of Service Merit from the Korean government in 2011 for his contributions to the Korean memory industry, the Scientist/Engineer of the month Award from the Ministry of Education, Science and Technology of Korea in 2010, and the Kyung-Am Scholar Award in 2014. He also received the Electronic Industrial Association of Korea Award for his contributions to the DRAM technology in 1994, the Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, the Best Research of KAIST Award in 2007, the Excellent Scholar of KAIST Award in 2011, and the Best Scholar of KAIST Award in 2019. In addition, he was a co-recipient of the ASP-DAC Design Award in 2001, the A-SSCC Outstanding Design Awards in 2005, 2006, 2007, 2010, 2011, and 2014. He was the recipient of the ISSCC/DAC Student Design Contest Awards in 2007, 2008, 2010, and 2011, the recipient of the ISSCC Demonstration Session Recognition in 2016, 2017, 2019, and the Best Paper Award of the IEEE AI-CAS in 2019. He has served as an Executive Committee member of the ISSCC, was IEEE SSCS Distinguished Lecturer ('10-'11), and was the TPC Chair of the International Symposium on Wearable Computers (ISWC) 2010 and the A-SSCC 2008. He was the Editor-In-Chief (EIC) of the Journal of Semiconductor Technology and Science (JSTS) (published by the Korean Institute of Electronics and Information Engineers) from 2015 to 2019. He was also guest editor of the IEEE Journal of Solid-State Circuits (JSSC) and the IEEE EEE Transaction on Biomedical Circuits and Systems -. He is currently an associate editor of JSSC and IEEE Solid-State Circuits Letters (SSCL).
Dr. Kou-Hung Lawrence Loh is a Corporate Senior Vice President and the Corporate Strategy Officer of MediaTek Inc. He oversees the company's Corporate Strategy and Central Engineering Group, responsible for engineering the company's SOCs and chipsets design, development and implementation activities for all MediaTek's product lines including mobile communication, application processors, wireless connectivity, analog mixed-signal/RF, intelligent devices such as consumer/entertainment, IOT, automotive, optical storage and wire-line communication based broadband/networking business. Dr. Loh is also serving as President of MediaTek USA, Inc., responsible for the company's global operations in Europe and America. Dr. Loh started his first circuit design position at IMP and later he joined Cirrus Logic, where his last position was Director of Analog IC Engineering. In 1998, he founded Silicon Bridge Inc., where he successfully led a number of analog/mixed-signal IC development projects with major semiconductor companies including MediaTek and Altera Corporation. Before joining MediaTek in 2004, he contributed to IC design industry in areas of read/write channels for magnetic and optical storage, high-performance analog filters, solid-state fingerprint sensors, high speed SERDES and wireline transceivers for various business applications. Dr. Loh received his Ph.D. degree in Electrical Engineering from Texas A&M University, College Station, Texas. He has contributed to numerous IEEE SSCS activities throughout his 32 years of membership. Dr. Loh has authored/co-authored dozens of technical papers/patents in areas of integrated circuits and systems design. He served on the ISSCC ITPC between 2005-2010. In the past decade, Dr. Loh had been the keynote/plenary speaker at major IEEE Conferences such as A-SSCC, RFIC, IWS, MWSCAS, etc. He also contributed to multiple panel talks, forum presentations, and invited talks at numerous international conferences and professional communities, including ISSCC and VLSI Symposium. Dr. Loh is the recipient of APSIPA Industrial Distinguished Leader Award in 2015. He is currently serving on the Steering Committee of A-SSCC and also on Board of Directors for Global Semiconductor Alliance (GSA).
Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001. He was a research associate at Hiroshima University from 1994 to 2002, an associate professor at Kobe University from 2002 to 2009, and was promoted to a full professor in 2009. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.His research interests include design techniques targeting high-performance mixed analog, RF, and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety. He was a co-recipient of the best paper awards from IEEE 3D-Test 2013, IACR CHES 2014 and IEEE APEMC 2015. Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009), Custom Integrated Circuits Conference (2007-2009), Asian Solid-State Circuits Conference (2005-2009), International Solid-State Circuits Conference (2014-2017) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He was a technical program chair (2010-2011), a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits. Dr. Nagata was also the chair for IEEE SSCS Kansai Chapter (2017-2018). He is currently an associate editor for the IEEE Transactions on VLSI Systems (2015-present).
Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993, and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now is a professor at the VLSI Design and Education Center, the University of Tokyo. He is also a professor at the department of electrical engineering and information systems, graduate school of engineering, the University of Tokyo, where he served as a department head in 2017. He was also a visiting Researcher at Cambridge University in 2001. He has been involved in the activities of VDEC to promote VLSI design educations and researches in Japanese academia. He initiated “AI chip design project” for Japanese startups, supported by Ministry of Economy, Trade and Industry (METI) of Japan. His research topics including hardware security, smart image sensor for 3-D range finding, and time-domain circuits including asynchronous controlling and associate memories. He has published more than 230 technical publications, including 10 invited papers, and 7 books/chapters. He served as a Distinguished Lecturer of the IEEE SSCS for 2015 and 2016, IEEE SSCS Japan Chapter Chair (2017-2018), IEEE Japan Council, and Chapter Operation Committee Secretary (2007-2008). He was a member of the ISSCC Executive Committee (’09-’13), FE Regional Sub-committee Chair (’13) , Vice-Chair(’11-’12). Secretary(’09-’10), ITPC IMMD sub-committee member(’06-’18), Sub-committee chair(’15-’18 ), ITPC Vice Chair (‘20) & ITPC Chair (‘21), SRP/Student Forum(’08-) Sec.(’08-’09), co-chair (’10-’12, ’19). He served on the VLSI Circuits Symposium Executive Committee, (’16-’19), was a Program Committee member(’99-’17), Chair(’16-’17), Sec.(’12-’15), and Symposium Chair (’18-’19). For the Asian Solid-State Circuits Conference (A-SSCC), he was a TPC member(‘05-’15), TPC Chair(‘15), TPC Vice Chair(‘05), Steering and Committee Member (‘15-). For the European Solid-State Circuits Conference (ESSCIRC), he was a Program Committee Member (‘18-). He was also a Guest Editor for the IEEE Journal of Solid-State Circuits for the following issues: 2006 Nov.(A-SSCC 2005 Special Section), 2015 Oct. (A-SSCC 2014 Special Section), 2017 April (VLSI Circuits 2016 Special Issue), and 2018 April (VLSI Circuits 2017 Special Issue).He is a senior member of IEEE, a senior member of IEICE, and a member of ACM and IPSJ.
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 284 publications in refereed international conferences and journals with a citation H-index of 77, and 226 patents issued with 29 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He is the recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award. He received 4 Best Paper awards and nominations, and the Outstanding Evening Session Award at 2018 ISSCC. One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the "Top 10 Cited Papers in 50 Years of DAC", and another one received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Prolific Contributor to ISSCC at its 60thAnniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He served as SSCS Distinguished Lecturer 2017-18 and as EDS Distinguished Lecturer in 2011. He served in the ISSCC Technical Program Committee 2014-2019 and is currently serving in the 2020 ISSCC Forums Committee. He was a member of the Technical Program Committee of the IEEE Symposium on VLSI Circuits 2004-2014, serving as the Technical Program Chair 2011-12, General Chair 2013-14, and a member of the Executive Committee since 2015. He has been an Associate Editor of the IEEE Journal of Solid-State Circuits since 2014, and served as Associate Editor of IEEE Transactions on VLSI Systems 2011-2015 and IEEE Transactions on Circuits & Systems I 2008-2010. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.
Woogeun Rhee is a Professor in the Institute of Microelectronics and the Department of Microelectronics and Nanoelectronics at Tsinghua University, Beijing, China. He has over 20 years of a professional career in integrated circuit design with nearly 10 years in industry and 13 years in academia. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and developed the industry’s first 20-pin package dual fractional-N/integer-N frequency synthesizer product (CX74038) in 2000. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking circuits for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. He developed the company’s first >10GHz PLL with 90nm bulk CMOS technology in 2001. In August 2006, he joined the faculty as an Associate Professor in the Institute of Microelectronics at Tsinghua University, Beijing, China, and became a Professor in December 2011. His current research interests include short-range low-power radios for next generation wireless systems and clock/frequency generation circuits for wireline and wireless communications. He has published >150 IEEE publications and given >10 tutorials at IEEE conferences, including ISSCC, CICC, A-SSCC, and ISCAS. He currently holds 23 U.S. patents. Dr. Rhee was a Distinguished Lecturer for the Solid-State Circuits Society for 2016-2017 and served as an Associate Editor for IEEE Transactions on Circuits and Systems II (TCAS-II) from 2008 to 2009, Journal of Solid-State Circuits (JSSC) from 2012 to 2018, and a Guest Editor for JSSC Special Issue in November 2012 and November 2013. He also served as a member of the Technical Program Committee for ISSCC from 2012 to 2016. He currently serves as the Technical Program Co-Chair of the 2019 International SoC Design Conference, the subcommittee Chair of A-SSCC, and the subcommittee Co-Chair of CICC. He received several outstanding awards when he was with Conexant Systems and IBM Watson Research Center. He was the recipient of the IBM Faculty Award from IBM Corporation in 2007 and the Advanced Employee Award from Tsinghua University in 2012. He received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001.
Andreia Cathelin (M’04, SM’11) started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France. Since 1998, she has been with STMicroelectronics, Crolles, France, now Technology R&D Fellow. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is as well one of the pioneers in FD-SOI CMOS design. Andreia has had numerous responsibilities inside the IEEE community since more than 10 years. At ISSCC, she has been the RF sub-committee chair from 2012 to 2015, and since 2016 is the Forums Chair and member of the Executive Committee. She has been the ESSCIRC-ESSDERC Steering Committee Chair from 2015 to 2017. During her mandate as ESSxxRC Steering Committee Chair, two major MoU’s have been signed with respectively SSCS and EDS societies, bringing now both conferences among the top ranked conferences in the respective fields, as financially fully sponsored events. This recognizes these conferences as the major yearly European R&D meeting place for the industry and academia communities. She has served different positions on the Technical Program Committees of VLSI Symposium on Circuits from 2010 till 2016, and is now member of its Executive Committee. She has been an elected member of the IEEE SSCS Adcom for the term January 2015 to December 2017, and is an active member of the IEEE SSCS Women in Circuits group. Andreia has authored or co-authored 130+ technical papers and 7 book chapters, and has filed more than 25 patents. Andreia is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company’s roadmap the integrated CMOS THz technology for imaging applications.