SSCS AdCom Election and Petition Processes
2020 SSCS AdCom Election for Term 2021-2023
Each year, the IEEE Solid-State Circuits Society (SSCS) rotates out the five Member-at-Larges whose term on the AdCom will be ending in December. This is done through the annual SSCS AdCom Election, which is organized by the SSCS Nominations Committee and Chaired by the current SSCS Past President. In 2020, the Chair is Bram Nauta and the election term is 2021-2023.
Below, you will find the slate for the 2021-2023 SSCS AdCom Member-at-Large Election. These individuals were nominated by both the General Membership of the Society and the current SSCS AdCom Members.
Petition Process for AdCom Election Term 2021-2023
2021-2023 Member-at-Large AdCom Slate
Dina El-Damak received a B.Sc. degree from Ain Shams University, Egypt in 2007, and the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 2012 and 2015 respectively. She is currently an assistant professor of Electrical and Computer Engineering at the Viterbi School of Engineering at USC, where she focuses on the design of hardware for machine learning applications, energy harvesting, and power management circuits.
She is a senior member of IEEE.
Additionally, she has been a member of the Technical Program Committee of the IEEE Custom Integrated Circuits Conference and the Women in Circuits Committee since 2019. She is the co-chair of the Power Management Subcommittee of IEEE CICC 2020.
Don Draper is a Contributing Tech Writer at SemiWiki, The Next Platform and is Principal Analyst of ProPrincipia International Associates, based in Cupertino, California consulting in STT-MRAM, 3D Integrated Circuits, Integrated Voltage Regulators, and server processor physical architecture. He is also a member of the SEMI Standards Committee for 3D Packaging and Integration. He was formerly at Oracle Corporation as Senior Principal Hardware Engineer working on circuit design and physical architecture of server processors, specifically 3DIC implementation and Integrated Voltage Regulators. Previous positions included Design Manager at Rambus, Inc and Circuit Design Manager and Fellow at Advanced Micro Devices developing high-performance microprocessors.
IEEE activities include SSCS Conferences committee, member for several years on the Program Committee of the International Solid-State Circuits Conference (ISSCC), Chairman of the IEEE Computer Society Technical Committee for Microcomputers and Microprocessors (TCMM), for four years, Hot Chips General Chair in 2008, Steering Committee for the Hot Chips Conference, Steering Committee and co-General Chair of the Hot Interconnects Symposium for 2019 and 2020. He graduated from the University of British Columbia, Vancouver, Canada with a Bachelor of Applied Science in Engineering Physics and from Carleton University in Ottawa, Canada with a Masters in Engineering in Semiconductor Physics.
Ichiro Fujimori received the B.S. degree in Electrical Engineering from the Tokyo University of Science in 1985, and the PhD degree from the University of Hiroshima in 2003. In 1985, Dr. Fujimori joined Asahi-Kasei Microsystems (AKM), Japan. His pioneering work includes the industry first Delta-Sigma DAC for portable audio achieving 90-dB dynamic range at 1.5-V operation, and the first Delta-Sigma ADC for professional audio exceeding 123-dB dynamic range. In 2000, he joined Newport Communications (later acquired by Broadcom). As the Manager of Mixed-Signal Engineering, he led the team to the development of the first CMOS transceiver LSI’s for SONET OC-192 applications, and the first IEEE 802.3ae “10GE LAN PHY” SOC where the 10-Gbps transceivers and the sub-layer system (XAUI) were integrated on the same chip. In 2012, he was appointed Vice President of Central Engineering at Broadcom Corporation, responsible for the roadmap and development of mixed-signal IP that enables Communication SoCs for both Consumer and Network Infrastructure applications. The IP include multi-gigabit SerDes for Networking, Optical transceivers, Ethernet Copper PHYs, Automotive AFEs, PLL’s, mobile PMU, Power-Over-Ethernet and embedded Power Management circuits. He is currently the Vice President of R&D at the Mixed Signal ASIC Product Division of Broadcom Incorporated (Avago/Broadcom merger), leading the analog ASIC development for Mobile Platforms, Satellite Communications and 5G Base-Stations.
Dr. Fujimori is an IEEE Fellow, and the recipient the IEEE Journal of Solid-State Circuits, Best Paper Award 2000 for the paper entitled “A Multi-bit Delta-Sigma Audio DAC with 120-dB Dynamic Range.” He has published 40 technical articles including 11 ISSCC papers, and has conducted various Seminars, Invited talks, and Panels in the field of Data Converters and Wireline Communications. He has served in the Technical Program Committee of VLSI Circuits Symposium from 2009 to 2014, and in the Executive Committee since 2015. He served in the Technical Program Committee of International Solid State Circuits Conference from 2011 to 2017, and the Associate Editor of the IEEE Journal of Solid-State Circuits from 2012 to 2018. He is currently in the IEEE SSCS Fellow Evaluation Committee. He holds 35 U.S. patents.
Ana Sonia Leon is an industry recognized and sought-after technical expert with 25+ yrs. of industry experience in the field of SOC Design and Silicon Technology, with the unique expertise and passion for bridging the gap between Product architecture, silicon, design and Tools-Flows-Methodology through their simultaneous co-optimization. Sonia is currently responsible for the Technology readiness and pathfinding for Intel’s new generation of FPGA Product solutions. Before that, Sonia was also responsible for pathfinding holistic co-optimization solutions which enabled full Product KPI’s competitiveness for Intel’s wireless and connectivity products in Intel’s and external foundries advanced silicon technology.
Prior to joining Intel in 2010, Sonia was with Oracle/Sun Microsystems for 12yrs where she served as a Senior Principal Engineer and Director of Technology, responsible for defining holistic design platforms in advanced technologies, as well as Sun’s strategic joint efforts with the industry eco system (Foundry, EDA, and Product). She also directed the design of several high-performance SPARC Processors, including the first generation of SPARC Chip-Multi-Threaded processors (UltraSparc T1), the dual-core UltraSPARC and the UltraSparc-IIe; being responsible for design technology and foundry interface, memories, analog, clocking, power, design methodology, product tapeout and qualification. Before joining Sun, Sonia was with Chromatic Research and Motorola where she was a Senior Circuit Designer and Project Lead in the development of Multimedia Chips and DSP Processors for Cellular. Sonia's interests are in the integration of advanced technologies and co-optimization across the full System stack for Server, Cloud Computing and Mobile. She has authored 16 papers in microprocessor design and holds 3 U.S patents in circuit design. She is a Senior Member of IEEE and served in the ISSCC Technical Program Committee, Forum’s and Industry Committees as well as Women in Circuits. Sonia received her MSEE from the University of Southern California in 1988 and BSEE from ESPOL (Ecuador).
Antonio Liscidini received the Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently an Associate professor. In 2019 he has become consultant for Huawei Technology Group in the area of RFIC for optical communication. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless and wireline communication.
Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits and co-recipient of the Best Invited Paper Award at the 2011 IEEE CICC and Best Student Paper Award at the 2018 IEEE ESSCIRC. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and Guest Editor of the IEEE RFIC Virtual Journal (2018). He has been member of the ISSCC TPC (2012- 2017), of the ESSCIRC TPC (2010-2018), and of the CICC TPC (2019-currently). Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society.
Rikky Muller (M’04–SM’17) received the B.S. and M.S. degrees from MIT, Cambridge, MA, USA, and the Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, all in electrical engineering and computer sciences (EECS). She previously held positions as an IC Designer with Analog Devices, Wilmington, MA, USA, and as a McKenzie Fellow and a Lecturer of EE with the University of Melbourne, Melbourne, VIC, Australia. She was also the Co-Founder of Cortera Neurotechnologies, Inc., Berkeley, a medical device company founded in 2013 and acquired in 2019, where she held positions as CEO and CTO. She is currently the S. Shankar Sastry Assistant Professor in Emerging Technologies with the EECS Department, University of California at Berkeley. She is also the Co-Director of the Berkeley Wireless Research Center, a Core Member of the Center for Neural Engineering and Prostheses, University of California at Berkeley, and an Investigator with the Chan-Zuckerberg Biohub, San Francisco, CA, USA. Her expertise is in the research and commercialization of implantable medical devices and in developing integrated circuits (ICs) and systems for neurological applications.
Dr. Muller is a member of the technical program committee for IEEE ISSCC, and has previously served on the committees of IEEE CICC and BioCAS. She has also served as a Guest Editor for the IEEE Journal of Solid-State Circuits. She is a Senior Member of the IEEE, and a member of the Solid-State Circuits Society, the Circuits and Systems Society, the Society for Neuroscience, Women in Circuits and Women in Neural Engineering. She has received numerous fellowships and awards, including the National Academy of Engineering Gilbreth Lectureship, the Chan-Zuckerberg Biohub Investigatorship, the Keysight Early Career Professorship, the Hellman Fellowship, and the NSF CAREER Award. She was named one of MIT Technology Review’s top 35 global innovators under the age of 35 (TR35), and one of MedTech Boston’s top 40 healthcare innovators under 40.
Kazuko Nishimura received the B.E. degree in mechanical engineering from Osaka University, Japan, in 1995. In 1995, she joined the Semiconductor Research Center, Panasonic Corporation where she had been engaged in the research and development of high-speed ADCs. Her team developed ultra high-speed ADCs  and contributed for a lot of digital read channel applications. From 1998 to 2007, she had joined the task force of optical communication systems, and developed FTTH (Fiber to the home) systems. Her team developed Gbit/s-class CMOS Burst-Mode Optical Transceivers . From 2009 to 2012, she had been engaged in the research and development of RF systems. Her team developed Industry's-first LSI that integrated one-seg tuner and demodulation function.
From 2006 to 2014, she had been engaged in the research and development of CMOS image sensors and contributed to the mass productions of various cameras. Now, she is a Manager in Technology Innovation Division (R&D research division), Panasonic Corporation and has been engaged in the research and management of organic photoconductive film CMOS image sensors and sensor applications . She has authored and co-authored 7 international journal papers and conference papers. She holds more than 50 patents.
Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. From 1997 to 2000, he was with Texas Instruments in Warren, New Jersey, where he worked on high speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks in Sunnyvale, California.
Since July 2002, he has been with the Indian Institute of Technology-Madras, where he is now a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design and signal processing.Dr.~Pavan is the recipient of several awards, and is the author of "Understanding Delta-Sigma Data Converters (second edition)" with Richard Schreier and Gabor Temes. Dr.Pavan has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I - Regular Papers. He has served on the technical program committee of the International Solid State Circuits Conference, and has been a Distinguished Lecturer of the Solid-State Circuits and CAS Societies. He serves as an Associate Editor of IEEE Solid-State Circuits Letters. He is a fellow of the Indian National Academy of Engineering, and an IEEE fellow.
Elkim Roa has been working on solid-state circuits design since 2003. Although Elkim is not an industry veteran and neither a full professor with many accolades, he has been in the industry and academy for some time. Time enough to understand what we can do to foster young leaders motivated in solid-state circuits. Elkim received his B.E.E. from Universidad Industrial de Santander, Colombia, and his M.S.degree from the University of São Paulo, São Paulo, Brazil. He received a Ph.D. degree in electrical engineering from Purdue University, where he was a Fulbright Scholar. From 2014 to 2016, he was with Rambus, Inc., where he was engaged in high-speed SERDES front-end design. Since 2016 he has been an Associate Professor at Universidad Industrial de Santander. His research interests include circuits and architecture design for security, front-end circuits for high-speed interfaces, and low-energy and efficient computing. He is the director of the only research group in solid-state circuits in Colombia, the OnChip research group. Three generations of full SoC RISC-V based, including the first RISC-V based microcontroller in 2016, have been successfully designed and tested during the short 4-years group history. Elkim was part of the team that launched a crowdfunding campaign to fund the development of a full SoC, resulting later in many teams around the world working on similar endeavors. He has authored and co-authored over 30 conference/journal publications. He holds two patents and has six pending patents in the area of integrated circuits. He has served as a reviewer of IEEE Transactions on Microwave Theory and Techniques, IEEE Journal of Solid-State Circuits, and IEEE Transactions on Circuits and Systems. He currently serves as a technical program committee member of the IEEE Custom Integrated Circuits Conference (CICC).
Farhana Sheikh (IEEE SM 2014, IEEE M 1993) received the B.Eng. degree in Systems and Computer Engineering with high distinction and Chancellor’s Medal from Carleton University, Ottawa, Canada, in 1993 and the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1996 and 2008, respectively. From 1993 to 1994 she worked at Nortel Networks as a software engineer in firmware and embedded system design. From 1996 to 2001, she was at Cadabra Design Automation as software engineer and senior manager. She joined Intel Labs in 2008 as Senior Research Scientist and Staff Scientist in the Circuit Research Lab. In 2014, she led the Digital Communications Lab as Senior Staff Scientist and Research Manager. In October 2016, after her Intel sabbatical, she joined Radio Circuits Technology Lab and expanded her research into mixed-signal circuits for communication. In November 2018, Dr. Sheikh joined Intel’s Programmable Solutions Group CTO and Strategy Office as Senior Staff Scientist. Farhana’s research interests include FPGA and chiplet co-packaging, smart chiplets leveraging machine learning and artificial intelligence, low-power digital and mixed-signal CMOS design, circuits and systems for advanced wireless communication, wireless security, cryptography, signal/image processing, and design of intelligently adaptive radio systems. Farhana has co-authored over 40 publications in VLSI circuit design, including editing and co-authoring Circuits and Systems for Security and Privacy.
Farhana has filed over 20 patents on wireless communication SoCs, cryptography hardware accelerators, and 3-D graphics circuits at Intel Corporation. Dr. Sheikh was a recipient of the Association of Professional Engineers of Ontario Gold Medal for Academic Achievement, the NSERC’67 scholarship for graduate studies, and the Intel Foundation Ph.D. Fellowship. In 2012, she was a co-recipient of the ISSCC Distinguished Technical Paper award. In 2020, she was a co-recipient of the ISSCC Lewis Award for Outstanding Paper, and ISSCC Demonstration Session Certificate of Recognition. Farhana is the IEEE SSCS Oregon Chapter Chair since 2017; and serves on multiple IEEE SSCS TPC committees. She has been an active contributor to the IEEE SSCS Women in Circuits (WiC) Committee and was Co-Chair of the IEEE SSCS WiC Rising Stars 2020 Workshop at ISSCC 2020. She is also an active member of the IEEE Signal Processing Society (SPS) and has been on the TPC for multiple SPS conferences. She is the TPC Co-Chair for the IEEE 2020 SIPS Workshop to be held in October 2020.
Esther Rodriguez-Villegas is a Full Professor of Low-Power Electronics at Imperial College, originally known for her engineering techniques to drastically reduce power in integrated circuits. She subsequently focused her research on life-science applications, founding the Wearable-Technologies-Lab. This lab specializes on both: creating innovative wearable-medical technologies to improve management and diagnosis of chronic diseases; and neural interfaces to facilitate brain research whilst improving animals’ welfare.
Esther is also a founder, co-CEO and CSO, of two active life-sciences companies, Acurable and TainiTec. Esther has received many international recognitions and awards, including two European Research Council grants (2009 and 2016), a global XPRIZE-award (2014), and a global AAALAC 3Rs award for Europe (2018). She was also named the top scientist/engineer in Spain under the age of 36 in 2009 (Complutense award).
Hoi-Jun Yoo is is an IEEE fellow and the ICT Chair professor of School of Electrical Engineering and the director of the System Design Innovation and Application Research Center (SDIA) at KAIST. He is the Chair of Steering Committee of A-SSCC (2020-2024), and was the TPC Chair of ISSCC 2015, and a Plenary Speaker of ISSCC 2019 entitled “Intelligence on Silicon: From Deep Neural Network Accelerators to Brain-Mimicking AI-SoCs”. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and TPC Chairs of International Symposium on Wearable Computers (ISWC) 2010 and A-SSCC 2008. He was a guest editor of IEEE JSSC and IEEE T-BioCAS, and is an associate editor of IEEE JSSC and SSCL. His current research interests are Bio Inspired AI Chip Design, Multicore AI-SoC design including DNN accelerators, Network on a Chip, and high speed and low power memory.
He has published more than 250 papers, and wrote or edited 5 books “DRAM Design”(1997, Hongneung). “High Performance DRAM”(1999 Hongneung), “Low Power NoC for High Performance SoC Design”(2008, CRC), “Mobile 3D Graphics SoC”(2010, Wiley), and “BioMedical CMOS ICs”(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books. Dr. Yoo received the Order of Service Merit from Korean President in 2011 for his contribution to Korean memory industry, the Scientist/Engineer of the month Award from Ministry of Education, Science and Technology of Korea in 2010, Kyung-Am Scholar Award in 2014. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, Excellent Scholar of KAIST Award in 2011, Best Scholar of KAIST Award in 2019, and was a co-recipient of ASP-DAC Design Award in 2001, A-SSCC Outstanding Design Awards in 2005, 2006, 2007, 2010, 2011, 2014, ISSCC/DAC Student Design Contest Awards in 2007, 2008, 2010, 2011, and ISSCC Demonstration Session Recognitions in 2016, 2017, 2019, 2020, and Best Paper Award of IEEE AI-CAS in 2019.