Publications
SSCS proudly sponsors six top-notch publications as complimentary member benefits in print and electronic formats. The IEEE Journal of Solid-State Circuits (JSSC) - historically one of the top-five downloaded technical journals on IEEE Xplore - is available on-line and in print. The electronic-only Solid-State Circuits Letters (SSC-L) is a brief format companion to the JSSC that offers fast turnaround to authors for the latest innovations in our field. The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) - an open-access monthly accessible free of charge via IEEE Xplore - offers researchers a journal to publish and extend their research results with supplementary technical materials. Our newest open-access journal, IEEE Open Journal of Solid-State Circuits launches in Fall 2020.
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Shanthi Pavan Vice President of Publications |
Members also receive the IEEE Solid-State Circuits Magazine free of charge (in print and on-line), which is a tutorial-level quarterly featuring pioneering breakthroughs, trending topics, and “who’s who” reports about IC community leaders and international, regional, and local award recipients. Other electronic-only publications are the RFIC Virtual Journal, a one-stop, curated compilation of RFIC papers within the publications library of the IEEE, and IEEE Design & Test Magazine, which offers insight into models, methods and tools for microelectronic systems.
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits
- Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter
- A 200-
W Interface for High-Resolution Eddy-Current Displacement Sensors - A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation
- A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring
- An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
- A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS
- Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
- RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator
- Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition
- A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage
- A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
- MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices
- A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon Processor
- A High-Linearity and Low-EMI Multilevel Class-D Amplifier
- An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques
- A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3
Inaccuracy of 0.02, 0.12 for Battery-Monitoring Applications - A 440-W, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
- An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information
- Special Topic on Coupled Oscillators for Non-von Neumann Computation
- Understanding the Continuous-Time Dynamics of Phase-Transition Nano-Oscillator-Based Ising Hamiltonian Solver
- Noise Immunity of Oscillatory Computing Devices
- Convolution Inference via Synchronization of a Coupled CMOS Oscillator Array
- 2020 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 6
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
See more issues of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
- Staff List
- [Contributors]
- Welcome to the Winter 2021 Issue of IEEE Solid-State Circuits Magazine [Editor?s Note]
- A Year of Working Together [President's Corner]
- The Design of a Bootstrapped Sampling Circuit [The Analog Mind]
- The Resistor-Capacitor Circuit [Circuit Intuitions]
- Errata
- Paul Brokaw: IEEE Donald O. Peterson Award Winner
- Brokaw Bonus Tracks: A Few Lesser-Known Tunes
- References Supplied on Request: Paul Brokaw's Stamp on Analog IC Design
- Paul Brokaw, Jedi Master: Lessons From a Wizard
- Exploring Multimode Cellular Transceiver Design: A Short Tutorial
- Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture
- Memories of James D. Meindl: A Tribute [People]
- Dreamer of the Art of the Possible [People]
- Child-Like Curiosity and Enthusiasm [People]
- Three Outstanding Merits of Meindl's Career: A Personal View [People]
- A Model of Leadership, Kindness, and Humility [People]
- "Impossible" Problems, Unexpected and Powerful Outcomes [People]
- A Visionary and Nurturer [People]
Aims & Scope - This new electronic publication provides relevant references pertaining to RFIC technology, paired with value-added editorial commentary from technology experts. The RFIC Virtual Journal aims to be the leading focal point on radio frequency integrated circuits from a worldwide perspective by collecting and disseminating knowledge on theory; enabling technologies, design methodologies, fabrication, testing of radio frequency integrated circuits, and systems; and determining which process signals to be transmitted or received through wireless communication.
To access this journal content have your IEEE Xplore login information ready and click here.
- Editorial Welcome to the New Editor-in-Chief
- A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process
- 10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV
V MIN Reduction With Negligible Active Power Overhead - A 9-bit, 45 mW, 0.05 mm2 Source-Series-Terminated DAC Driver With Echo Canceller in 22-nm CMOS for In-Vehicle Communication
- A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors
- High Slew-Rate Quadruple-Voltage Mixed-Quenching Active-Resetting Circuit for SPADs in 0.35-
m CMOS for Increasing PDP