Publications
SSCS proudly sponsors six top-notch publications as complimentary member benefits in print and electronic formats. The IEEE Journal of Solid-State Circuits (JSSC) - historically one of the top-five downloaded technical journals on IEEE Xplore - is available on-line and in print. The electronic-only Solid-State Circuits Letters (SSC-L) is a brief format companion to the JSSC that offers fast turnaround to authors for the latest innovations in our field. The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) - an open-access monthly accessible free of charge via IEEE Xplore - offers researchers a journal to publish and extend their research results with supplementary technical materials. Our newest open-access journal, IEEE Open Journal of Solid-State Circuits launches in Fall 2020.
|
Shanthi Pavan Vice President of Publications |
Members also receive the IEEE Solid-State Circuits Magazine free of charge (in print and on-line), which is a tutorial-level quarterly featuring pioneering breakthroughs, trending topics, and “who’s who” reports about IC community leaders and international, regional, and local award recipients. Other electronic-only publications are the RFIC Virtual Journal, a one-stop, curated compilation of RFIC papers within the publications library of the IEEE, and IEEE Design & Test Magazine, which offers insight into models, methods and tools for microelectronic systems.
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)
- A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
- A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control
- 10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture
- A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-
N MDLL in 22-nm FinFET CMOS - A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique
- NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics
- IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
- Cores, Cache, Content, and Characterization: IBMs Second Generation 14-nm Product, z15
- A 1.5-
J/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots - A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing
- EM and Power SCA-Resilient AES-256 Through 350 Current-Domain Signature Attenuation and Local Lower Metal Routing
- A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS
- STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete SpinSpin Interactions
- A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-
V MIN Applications - A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
- A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
- An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
- A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg 75
s and tR 4 s
- IEEE Journal on Exploratory Solid-State Computational Devices and CircuitsVolume 6, No. 2
- Temporal Memory With Magnetic Racetracks
- Experimental Demonstration of a Reconfigurable Coupled Oscillator Platform to Solve the Max-Cut Problem
- Energy-Efficient Ferroelectric Field-Effect Transistor-Based Oscillators for Neuromorphic System Design
See more issues of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
- Staff List
- [Contributors]
- Welcome to the Winter 2021 Issue of IEEE Solid-State Circuits Magazine [Editor?s Note]
- A Year of Working Together [President's Corner]
- The Design of a Bootstrapped Sampling Circuit [The Analog Mind]
- The Resistor-Capacitor Circuit [Circuit Intuitions]
- Errata
- Paul Brokaw: IEEE Donald O. Peterson Award Winner
- Brokaw Bonus Tracks: A Few Lesser-Known Tunes
- References Supplied on Request: Paul Brokaw's Stamp on Analog IC Design
- Paul Brokaw, Jedi Master: Lessons From a Wizard
- Exploring Multimode Cellular Transceiver Design: A Short Tutorial
- Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture
- Memories of James D. Meindl: A Tribute [People]
- Dreamer of the Art of the Possible [People]
- Child-Like Curiosity and Enthusiasm [People]
- Three Outstanding Merits of Meindl's Career: A Personal View [People]
- A Model of Leadership, Kindness, and Humility [People]
- "Impossible" Problems, Unexpected and Powerful Outcomes [People]
- A Visionary and Nurturer [People]
Aims & Scope - This new electronic publication provides relevant references pertaining to RFIC technology, paired with value-added editorial commentary from technology experts. The RFIC Virtual Journal aims to be the leading focal point on radio frequency integrated circuits from a worldwide perspective by collecting and disseminating knowledge on theory; enabling technologies, design methodologies, fabrication, testing of radio frequency integrated circuits, and systems; and determining which process signals to be transmitted or received through wireless communication.
To access this journal content have your IEEE Xplore login information ready and click here.
- Editorial Welcome to the New Editor-in-Chief
- A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process
- 10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV
V MIN Reduction With Negligible Active Power Overhead - A 9-bit, 45 mW, 0.05 mm2 Source-Series-Terminated DAC Driver With Echo Canceller in 22-nm CMOS for In-Vehicle Communication
- A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors
- High Slew-Rate Quadruple-Voltage Mixed-Quenching Active-Resetting Circuit for SPADs in 0.35-
m CMOS for Increasing PDP