Publications
SSCS proudly sponsors six top-notch publications as complimentary member benefits in print and electronic formats. The IEEE Journal of Solid-State Circuits (JSSC) - historically one of the top-five downloaded technical journals on IEEE Xplore - is available on-line and in print. The electronic-only Solid-State Circuits Letters (SSC-L) is a brief format companion to the JSSC that offers fast turnaround to authors for the latest innovations in our field. The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) - an open-access monthly accessible free of charge via IEEE Xplore - offers researchers a journal to publish and extend their research results with supplementary technical materials. Our newest open-access journal, IEEE Open Journal of Solid-State Circuits launches in Fall 2020.
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Shanthi Pavan Vice President of Publications |
Members also receive the IEEE Solid-State Circuits Magazine free of charge (in print and on-line), which is a tutorial-level quarterly featuring pioneering breakthroughs, trending topics, and “who’s who” reports about IC community leaders and international, regional, and local award recipients. Other electronic-only publications are the RFIC Virtual Journal, a one-stop, curated compilation of RFIC papers within the publications library of the IEEE, and IEEE Design & Test Magazine, which offers insight into models, methods and tools for microelectronic systems.
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Guest Editorial 2022 Custom Integrated Circuits Conference
- A 9151220 TOPS/W, 9761301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors
- T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
- An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache
- A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier
- A 72-fs-Total-Integrated-Jitter Two-Core Fractional-
N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner - A 2340-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA
- A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET
- A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter
- Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression
- A Highly Integrated Hybrid DCDC Converter With nH-Scale IPD Inductors
- A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current
- Fully Integrating a 400 V-to-12 V DCDC Converter in High-Voltage CMOS
- A Series-Parallel Switched-Photovoltaic DCDC Converter
- Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling
- A 112-Gb/s 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
- A 20-
s Turn-On Time, 24-kHz Resolution, 1.5100-MHz Digitally Programmable Temperature-Compensated Clock Generator - A 1.8G Input-Impedance 0.15V Input-ReferredRipple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction
- A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation
- Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths
- Self-Reset Schemes for Magnetic Domain Wall-Based Neuron
- Review of Magnetic Tunnel Junctions for Stochastic Computing
- High-Density SpinOrbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist
- Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions
See more issues of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
- IEEE Collabratec
- Masthead
- [Contributors]
- Welcome to the Winter 2023 Issue of
IEEE Solid-State Circuits Magazine [Editors Note] - Closing the Gender Gap in Our Field [Presidents Corner]
- IEEE Connecting
- The Design of a Transimpedance Amplifier [The Analog Mind]
- IEEE Feedback
- The Plan B Toolkit: Debug a high-speed ADC using decimation [Shop Talk: What You Didnt Learn in School]
- Voltage Follower, Part II [Circuit Intuitions]
- Circuits for Security and Secure Circuits: Implementation of cryptographic algorithms
- Analog Techniques for Digital Security: My gratitudes to visionary discussions
- Security Analysis of IoT Devices: From the system level to the logic level
- Preventing a Cryptoapocalypse: From mathematics to circuits for postquantum cryptography
- Through the Looking GlassThe 2023 Edition: Trends in solid-state circuits from ISSCC
- IEEE Proceedings
- ESSCIRC 2022 Hosts Fully In-Person Mentoring Event [Society News]
- SSCS Chapter Chairs Gather at ESSCIRC 2022 [Society News]
- SCS PICO Chronicles: A Processor With a 5-GHz Radio [Society News]
- [Errata]
Aims & Scope - This new electronic publication provides relevant references pertaining to RFIC technology, paired with value-added editorial commentary from technology experts. The RFIC Virtual Journal aims to be the leading focal point on radio frequency integrated circuits from a worldwide perspective by collecting and disseminating knowledge on theory; enabling technologies, design methodologies, fabrication, testing of radio frequency integrated circuits, and systems; and determining which process signals to be transmitted or received through wireless communication.
To access this journal content have your IEEE Xplore login information ready and click here.
- High-Efficiency 28-/39-GHz Hybrid Transceiver Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile Applications
- A 0.11-mW 2.4-GHz Receiver Employing a
Q -Boosted Impedance Transformer and Regenerative Amplifier Achieving 101-dBm Sensitivity and 28-dB SIR - A High-Output Power 1-V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology
- A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3 Lower-Refresh Frequency at a 2.5 Area Overhead in 28-nm FD-SOI
- A 0.24-
V-Input-Ripple 8- V-Input-Offset 10-MHz Chopper Operational Amplifier Employing MOS-DAC-Based Offset Calibration - A 16-Channel Low-Power Neural Connectivity Extraction and Phase-Locked Deep Brain Stimulation SoC