SSCS “PICO” Open-Source Chipathon

The IEEE Solid-State Circuits Society (SSCS) is pleased to announce the next edition of its open-source integrated circuit (IC) design contest under the umbrella of the PICO (Platform for IC Design Outreach) program. The OpenROAD Initiative is proud to sponsor Chipathon as part of its mission to foster and strengthen the OpenEDA ecosystem. The event is open to anyone (no restrictions), and we especially encourage participation by pre-college students, undergraduates, and underrepresented regions in the IC design community. This year’s SSCS PICO Open-Source Chipathon will culminate in a dedicated workshop where teams will present their designs, lessons learned, and, when available, silicon measurements through talks, posters, and demos. The workshop will emphasize reproducibility, reusable open-source building blocks, and transparent evaluation (verification artifacts and benchmark metrics), and will offer a paper option in conjunction with the workshop (details TBD).

This chipathon is designed to foster collaboration and accelerate the creation of reusable open-source IC building blocks and tooling contributions, targeting an open PDK ( GF180MCUD). Teams will be advised by experienced mentors and will work through the full flow from specification to tapeout-ready collateral.

Contest Outline (phased structure)

1. Sign up by [April, 2026].
2. Phase 1 (May): Onboarding + weekly training sessions + project introductions; teams formed by the end of phase 1.
3. Phase 2 (May/June): Mentored execution, tool setup, design flows, methodology, and meeting project specs.
4. Phase 3 (July): Formal design reviews for each team; feedback from experts.
5. Phase 4 (August/September): Final verification and integration; clean DRC/LVS and tapeout package submission by the shuttle deadline.
6. Phase 5 (post-tapeout): Silicon bring-up and measurements (where facilities are available); results added to the open repositories.
7. Phase Paper Submission

Participants will choose one track and work in teams under the guidance of volunteer mentors and track leads.

Track A — Foundational Building Blocks
Reusable IP and infrastructure blocks (analog/mixed-signal and digital) that are broadly useful across many chips. Build digital blocks using the OpenROAD toolchain for the RTL-GDS flow, along with other library characterization, digital, and AMS tools. These include blocks like adders, DSP datapath blocks, microcontrollers, FSMs, etc. Core analog and mixed-signal circuits and macros (e.g., Bandgap reference (BGR) with ZTAT/PTAT current source, Ring oscillator (possibly temp. compensated, 8-bit SAR ADC, 8-bit current steering DAC, amplifiers, memory blocks), with emphasis on robust verification and reusability.
Track Leads: James Stine, Saroj, Gaurav, Akhilesh Patil, Sumanth Kamineni

Track B — Circuits for Sensors
Develop analog/mixed-signal front-ends and edge processing circuits for applications like water quality monitoring, environmental sensing, healthcare, and smart infrastructure, with a focus on compact, autonomous systems. Approaching chiplet-based mentality where microelectronic circuits are designed as interfaces for distributed, edge-native systems that integrate MEMS, chemical/biological sensors, and CMOS to enable sparse, event-driven sensing, in-sensor processing, and TinyML at the edge—all with ultra-low-power operation.
Track Lead: Camilo Velez, Vipul Sharma, 

Track C — MOSbius – Playground for Chips
“Learn-by-measurement” designs (MOSbius-style chips) focused on broad accessibility and hands-on learning. Potential to include automation.
Track Lead: Peter Kinget, Juan Moya Baquero, Luighi

Track D — AI / LLM-assisted Circuits
This track focuses on AI/LLM-assisted workflows for developing tapeout-ready analog and digital circuits. Topics include agentic design flows, generator-based methodologies, design-space exploration, and reproducible analog/custom design approaches. Projects should demonstrate practical AI-assisted methods that accelerate and automate the IC design process, from specification and architecture exploration to RTL generation, circuit implementation, physical design, verification, and closure, with the goal of producing silicon-ready results.
Track Leads: Luighi, Mehdi Saligane, Saptarshi Ghosh, Gaurav, Osama Khan, Trio Adiono/Nur, Mauricio Montanares

Tooling and Reference Flow Committee: Mitch, Harald, Leo, Saroj, Mehdi, Peter, Vipul, Herman, Luighi

Logistics: John, Indira, Mitch  

By the tapeout deadline, each team should provide:

• A reproducible repository (open-source) including:
  • Specs, design documentation, and verification checklist
  • Netlists/layout (or generator scripts), testbenches, and simulation results
  • DRC/LVS-clean database for the block (or integrated macro)
• Integration collateral required by the chip-level template (details shared during the program)

After silicon returns (when feasible):

• Bring-up notes, measurement plan, measured results, and demonstration video added back to the project repo

We are exploring a venue where fabricated chips (and/or tapeout-ready results) will be presented:

• Target venue (TBD): [Conference / Workshop Name, Date, Location]
• Presentation format: poster/demo + short talk (TBD)
• Publication pathway (ideal): a peer-reviewed paper associated with the chipathon outcomes and a demo video (e.g., a special session, workshop proceedings, or companion paper track)

We will confirm the venue and paper submission details once the 2026 theme and partner conference are finalized.

• Open to all participants worldwide (no restrictions).
• Participation is expected to include weekly meetings and periodic reviews.
• No prior tapeout experience is required; mentorship is provided; however, the chipathon is not a training or a course.