IEEE Journal of Solid-State Circuits (JSSC)

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Aims and Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuit modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.

Membership in SSCS includes online access to the monthly Journal of Solid-State Circuits through IEEE Xplore. Use your IEEE Web account when you are asked to log-on. The JSSC is the most downloaded periodical IEEE hosts.

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Information for Authors

Introducing Overlength Page Charges

The Society Board has decided to implement overlength page charges to maintain the competitive and financial health of the Journal of Solid-State Circuits. The continued success of the Journal serves our technical community and keeps our flagship publication competitive within the IEEE family

Starting with papers submitted after October 1st, 2018, the SSCS will hence apply mandatory overlength page charges. This is irrespective of the page limits applied during submission, hence also applies to manuscripts that have obtained an exception for overlength submission. Charges are assessed when galley proofs are prepared, which is the last step before final publication in the Journal. Note that this could be slightly different from the formatting used by the authors during submission. If a manuscript exceeds ten pages in length, a mandatory overlength charge of $185 per page is applied beginning at the 11th page. The page will not include the last page of the paper if the last page consists only of reference and bios. Exceptions on this must be discussed with the Editor-in-Chief.

JSSC Zeitgeist

The most recent top 50 downloaded articles.

JSSC Bests

Dennis Sylvester

Dennis Sylvester

JSSC Editor-in-Chief

JSSC Papers on IEEE Xplore

Latest Issue

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Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium

 Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium 150 150

New Associate Editor

 New Associate Editor 150 150

Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting”

 Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting” 150 150

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits

 Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits 150 150

Guest Editorial 2023 Custom Integrated Circuits Conference

 Guest Editorial 2023 Custom Integrated Circuits Conference 150 150

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

 A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing 150 150

Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode

 Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode 150 150

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

 A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators 150 150

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

 A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking 150 150

Early Access

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A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality

 A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality 150 150

A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive $N$ -Path Filters

 A 125–600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive $N$ -Path Filters 150 150

A 16-MHz Crystal Oscillator With 17.5- $\mu$ s Start-Up Time Under 10 $^{4}$ -ppm- $\Delta $ F Injection Using Automatic Phase-Error Correction

 A 16-MHz Crystal Oscillator With 17.5- $\mu$ s Start-Up Time Under 10 $^{4}$ -ppm- $\Delta $ F Injection Using Automatic Phase-Error Correction 150 150

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling

 A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling 150 150

K/Ka-Band Hybrid-Packaged Four-Element Four-Beam Phased-Array Transmitter and Receiver Front-Ends With Optimized Beamforming Passive Networks

 K/Ka-Band Hybrid-Packaged Four-Element Four-Beam Phased-Array Transmitter and Receiver Front-Ends With Optimized Beamforming Passive Networks 150 150

A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching

 A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching 150 150

Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines

 Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines 150 150

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro

 Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro 150 150

A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch

 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch 150 150
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