IEEE Journal on Exploratory Solid-State Computational Devices and Circuits – Journals

  • No Comments

Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs

Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs 150 150
Author(s): Md. Hasan Raza Ansari, Bashayr Alqahtani, Naveen Kumar, Vihar Georgiev, Nazek El-Atab

Abstract:

This work highlights the potential application of raised source and drain (RSD) MOSFETs-based charge trapping memory (CTM) for next-generation computing applications. This simulation study presents a double-gate (DG)-RSD MOSFET technology with a short gate length (50 nm) to significantly improve the performance of logic-in-memory (LIM) and neuromorphic computing (NC) systems. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 197 – 204
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3630217
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression

Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression 150 150
Author(s): Md Rahatul Islam Udoy, Jack Hutchins, Shamiul Alam, Catherine Schuman, Ahmedullah Aziz

Abstract:

This article introduces a framework that establishes a cohesive link between the first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 179 – 187
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624662
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET 150 150
Author(s): Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 188 – 196
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624653
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A SPICE-Compatible Compact Model of Ferroelectric Diode

A SPICE-Compatible Compact Model of Ferroelectric Diode 150 150
Author(s): Musaib Rafiq, Mohammad Sajid Nazir, Ateeb Naseer, Yogesh Singh Chauhan, Shubham Sahay

Abstract:

In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing paradigms. We propose modified Schottky barrier and hopping models for capturing the on- and off-mode operations of the FE diode, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 166 – 170
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624212
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials

Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials 150 150
Author(s): Axel I. Saenz Rodriguez, Oksana Ostroverkhova, Pallavi Dhagat

Abstract:

We explore the effects of layered geometries of 2-D quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation of a 2-D quantum spin system with a shifted bilayer square lattice through the linear spin wave (LSW) approximation of quantum …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 171 – 178
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624217
Publisher: IEEE

View on IEEE Xplore

  • No Comments

1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations

1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations 150 150
Author(s): Imtiaz Ahmed, Akul Malhotra, Revanth Koduru, Sumeet Kumar Gupta

Abstract:

Ternary weight neural networks (TWNs), with weights quantized to three states (−1, 0, and 1), have emerged as promising solutions for resource-constrained edge artificial intelligence (AI) platforms due to their high energy efficiency with acceptable inference accuracy. Further energy savings can be achieved with TWN accelerators utilizing techniques such as compute-in-memory (CiM) and …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 157 – 165
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621160
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 150 150
Author(s): Piyush Kumar, Da Eun Shim, Azad Naeemi

Abstract:

This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 139 – 147
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621279
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs 150 150
Author(s): Sadik Yasir Tauki, Rudra Biswas, Rakesh Acharya, Jiahui Duan, Rajiv Joshi, Kai Ni, Vijaykrishnan Narayanan

Abstract:

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 148 – 156
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619908
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Non-Volatile ReRAM-Based Compact Event-Triggered Counters

Non-Volatile ReRAM-Based Compact Event-Triggered Counters 150 150
Author(s): Moin Diwan, Shengchao Zhang, Zidu Li, Alex James, Bhaskar Choubey

Abstract:

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 131 – 138
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619415
Publisher: IEEE

View on IEEE Xplore

Search this website