IEEE Journal of Solid-State Circuits

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A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture

A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture 150 150
Author(s): Xiaoyu Feng, Hedi Wang, Songran Xiao, Huazhong Yang, Yongpan Liu

Abstract:

Traditional 3-D Gaussian-splatting (3DGS) modeling relies on iterative optimization, leading to substantial latency and limited generalizability. Feedforward 3DGS alleviates these limitations by generating Gaussians through a single network inference. However, most existing processors are optimized for optimization-based 3DGS and do not fully exploit the distinct computational characteristics of feedforward 3DGS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737807
Publisher: IEEE

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A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs

A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs 150 150
Author(s): Jianxin Yang, Cheng Huang, Rui P. Martins, Xin Ming, Bo Zhang, Mo Huang

Abstract:

This article presents a modified hybrid Ladder converter for efficient energy recycling in low-duty-cycle systems-on-chip (SoCs) applications. Unlike the conventional schemes that recycle output-capacitor energy back to the battery, the proposed hybrid converter recycles energy into its own capacitors, eliminating battery-recharge losses and improving recycle/recharge efficiency. The design methodology …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738472
Publisher: IEEE

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A 20-mg mm-Scale Flying-Insect Localization Tag With Battery-Free Crystal-Less Burst-Mode Transmitter Achieving 1.45-km Range

A 20-mg mm-Scale Flying-Insect Localization Tag With Battery-Free Crystal-Less Burst-Mode Transmitter Achieving 1.45-km Range 150 150
Author(s): Yi Shen, Steve Young, Demba Komma, Ryan Strohman, Rahul Narasimha, Jeongtaek Chang, Andrea Bejarano-Carbo, Yunfan Wang, Guanren Tao, Hun-Seok Kim, David Blaauw

Abstract:

This article presents a 20-mg, battery-free, crystal-less transmitter (TX) tag for flying-insect localization, implemented in 28-nm CMOS. The tag consists of a TX chip, a co-designed $10~times ~5$ -mm loop antenna, photovoltaic (PV) cells, and three 10  $mu $ F 0201 multilayer ceramic capacitors (MLCCs) for energy storage. A capacitor-buffered burst-mode power architecture with …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737710
Publisher: IEEE

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150
Author(s): DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5409 – 5420
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712021
Publisher: IEEE

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications

A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications 150 150
Author(s): Xuliang Wang, Renwei Chen, Haoyu Wang, Yang Liu, Wing-Hung Ki, Yan Wang, Xiaosen Liu

Abstract:

This article presents a volumetric integrated voltage regulator (IVR) based on a switched-capacitor-stack-inductor (SCSL) architecture that employs a holistic topology-control-package codesign to overcome the hardware and efficiency bottlenecks of conventional asymmetric multiinductor designs. Based on a discrete-time state-space model, a rigorous root-locus analysis reveals that a rudimentary single voltage-mode control …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5825 – 5837
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713507
Publisher: IEEE

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Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques

Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques 150 150
Author(s): Ya Zhao, Runchen Wang, Lingao Huang, Haitao Ren, Jun Yin, Pui-In Mak, Li Geng, Chao Fan

Abstract:

This article reports a compact millimeter-wave (mm-wave) quad-core eight-phase oscillator featuring magnetic coupling and dual-injection coupling. Specifically, the quad-core oscillator is integrated in an LC-ring configuration via a windmill-shaping transformer for phase noise (PN) and chip area reduction. The eight-phase oscillator could eliminate the oscillation mode ambiguity and save the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5638 – 5650
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714874
Publisher: IEEE

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A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation

A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation 150 150
Author(s): Xuansheng Ji, Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Abstract:

This article presents a coherent polar phase-tracking receiver (PT-RX) for low-power Internet-of-Things(IoT) applications that supports Gaussian frequency-shift keying (GFSK), quadrature amplitude modulation (QAM), and amplitude phase shift keying (APSK). Existing single-path closed-loop receivers achieve low power but suffer from a fundamental tradeoff between loop stability and adjacent channel rejection (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5370 – 5382
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712802
Publisher: IEEE

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A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

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