IEEE Journal of Solid-State Circuits

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A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping 150 150
Author(s): Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu

Abstract:

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {,}-{,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668599
Publisher: IEEE

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Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation

Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation 150 150
Author(s): Hao Yu, Zhaojing Fu, Lianbo Liu, Qiang Zhou, Taiyun Chi, Sensen Li

Abstract:

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667125
Publisher: IEEE

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A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration

A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration 150 150
Author(s): Chang-Un Park, Jae-Hyun Chung, Chunsuk Kim, Hyun-Woo Shin, Charlie Tahar, Seung-Tak Ryu

Abstract:

This article presents a spur-suppressed background calibration technique for high-speed current-steering digital-to-analog converters (DACs), based on a paired current source (CS) switching scheme. In conventional background calibration, periodic switching of CSs to and from the calibration mode introduces unwanted glitches that appear as spurious tones. The proposed technique introduces an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668788
Publisher: IEEE

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A 350-pW Implantable Ventricular Arrhythmia Detection Engine With Bayesian Uncertainty Quantification in 65-nm CMOS

A 350-pW Implantable Ventricular Arrhythmia Detection Engine With Bayesian Uncertainty Quantification in 65-nm CMOS 150 150
Author(s): Zephan M. Enciso, Jianbo Liu, Boyang Cheng, Likai Pei, Steven Davis, Yifan Qin, Zhenge Jia, Xiaobo Sharon Hu, Yiyu Shi, Michael Niemier, Ningyuan Cao

Abstract:

Ventricular arrhythmias (VAs), particularly ventricular tachycardia and fibrillation, remain a leading cause of sudden cardiac death. Implantable cardioverter defibrillators (ICDs) can deliver life-saving shocks, but inappropriate shocks degrade patient outcomes and device efficiency. While deep learning has improved VA detection accuracy, it lacks uncertainty quantification (UQ), limiting clinical acceptability. This …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669040
Publisher: IEEE

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A 10–72 GHz SDR Receiver With Compact and Low-Phase-Noise LO Frequency Quintupler

A 10–72 GHz SDR Receiver With Compact and Low-Phase-Noise LO Frequency Quintupler 150 150
Author(s): Haoyu Bai, Ling Hao, Jiazheng Zhou, Han Huang, Dong Wang, Jiaqi He, Yifei Wang, Yipeng Wang, Junhua Liu, Huailin Liao

Abstract:

This article presents a wideband receiver (RX) operating in 10–72 GHz with multiprotocol coverage, which integrates the inductor-less local oscillator (LO) frequency quintupler for down-mixing. In the LO generator, phase interpolators (PIs) are implemented to obtain five-phase pulses. Then compact edge-combining switched-capacitor (SC) based frequency quintuple techniques are proposed to output …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669994
Publisher: IEEE

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Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency

Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency 150 150
Author(s): Sukbin Lim, Jung-Hoon Kim, Seungjae Moon, Junseo Cha, Dongjin Seo, Jongho Kim, Hunjong Lee, Jinwon Lee, Joo-Young Kim

Abstract:

The proliferation of large language models (LLMs) as cross-domain foundation models is fueled by aggressive scaling in both parameter counts and inference-time computation. The emergence of sophisticated reasoning models further accelerates this trend, demanding longer context windows and escalating the computational and memory burdens of inference. A fundamental challenge arises …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663603
Publisher: IEEE

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS

A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS 150 150
Author(s): Nayu Li, Ziyao Xiong, Botao Yang, Hang Lu, Yiwei Liu, Xiaokang Qi, Gaopeng Chen, Na Yan, Chunyi Song, Zhiwei Xu

Abstract:

This article presents a K/Ka-band transmit/receive (T/R) front-end for jointed sensing and communication (JSAC) applications. A reconfigurable matching network for both signal reception and transmission is realized using the proposed triple-coupled transformer (TCT) technique, achieving low power loss and a compact footprint. The T/R switch at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667736
Publisher: IEEE

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A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE

A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE 150 150
Author(s): Yudai Yamazaki, Yohei Morishita, Sunghwan Park, Takaya Uchino, Chenxin Liu, Jun Sakamaki, Akihiro Egami, Ryosuke Hasaba, Ken Takahashi, Tomoki Abe, Tomohiro Murata, Yoichi Nakagawa, Takashi Tomura, Hiroshi Taneda, Kei Murayama, Makoto Tsukahara, Hiroko Ota, Yoko Nakabayashi, Ryuji Kinugawa, Takumi Kojima, Anyi Tian, Kotaro Ito, Chun Wang, Hans Herdian, Yi Zhang, Zheng Li, Wenqian Wang, Hongye Huang, Dingxin Xu, Sena Kato, Michihiro Ide, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Koji Takinami, Kenichi Okada

Abstract:

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665184
Publisher: IEEE

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