IEEE Journal of Solid-State Circuits

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A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems

A Wide-Load-Range FVF-Based LDO With Adaptive Capacitor Amplifier and Ripple-Cancellation Technique for RF Systems 150 150
Author(s): Fangming Lou, Haoqiang Deng, Tuo Li, Kai Yuan, Ka Nang Leung, Junmin Jiang, Guoqing Li, Xun Liu

Abstract:

This article proposes a low-dropout regulator (LDO) using a flipped voltage follower (FVF) topology for wide-load-range and low-noise applications. The proposed LDO features a fast load transient response and wide-spectrum power-supply rejection (PSR) performance. To optimize frequency responses at light load and improve PSR performance in the mid-frequency band, an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3739837
Publisher: IEEE

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Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links

Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links 150 150
Author(s): Susnata Mondal, Sashank Krishnamurthy, Shuhei Yamada, Zhaokai Liu, Junyi Qiu, Soumya Bose, Zuoguo Wu, Gerald Pasdast, James Jaussi, Mozhgan Mansuri

Abstract:

This article presents a Universal Chiplet Interconnect Express (UCIe)-compliant die-to-die (D2D) transceiver PHY for chiplet interconnects over a standard organic package, along with an extension to off-package interconnects over printed circuit board (PCB) channels. The transceiver introduces several power-efficient, high-performance techniques, including an impedance-invariant passive continuous-time linear equalizer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737168
Publisher: IEEE

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A DTC-Less Fractional-N Sampling PLL With a Voltage-Domain Quantization Noise Cancellation Achieving 134-fs RMS Jitter

A DTC-Less Fractional-N Sampling PLL With a Voltage-Domain Quantization Noise Cancellation Achieving 134-fs RMS Jitter 150 150
Author(s): Hyogyoung An, Hyeonjun Nam, Changmin An, Heein Yoon

Abstract:

This work presents a 10-GHz fractional- $N$ sampling phase-locked loop (SPLL) that employs a voltage-domain quantization noise cancellation (QNC) technique. By eliminating the need for complex digital calibration blocks, the proposed architecture significantly reduces design complexity and system overhead typically associated with QNC for fractional- $N$ operations. A linear and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3741508
Publisher: IEEE

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150
Author(s): DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5409 – 5420
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712021
Publisher: IEEE

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications

A 0.73 A/mm3 Switched-Capacitor-Stack-Inductor Volumetric Integrated Voltage Regulator With Auxiliary-Assisted Gain Boosting for High-Power-Density PoL Applications 150 150
Author(s): Xuliang Wang, Renwei Chen, Haoyu Wang, Yang Liu, Wing-Hung Ki, Yan Wang, Xiaosen Liu

Abstract:

This article presents a volumetric integrated voltage regulator (IVR) based on a switched-capacitor-stack-inductor (SCSL) architecture that employs a holistic topology-control-package codesign to overcome the hardware and efficiency bottlenecks of conventional asymmetric multiinductor designs. Based on a discrete-time state-space model, a rigorous root-locus analysis reveals that a rudimentary single voltage-mode control …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5825 – 5837
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713507
Publisher: IEEE

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Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques

Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques 150 150
Author(s): Ya Zhao, Runchen Wang, Lingao Huang, Haitao Ren, Jun Yin, Pui-In Mak, Li Geng, Chao Fan

Abstract:

This article reports a compact millimeter-wave (mm-wave) quad-core eight-phase oscillator featuring magnetic coupling and dual-injection coupling. Specifically, the quad-core oscillator is integrated in an LC-ring configuration via a windmill-shaping transformer for phase noise (PN) and chip area reduction. The eight-phase oscillator could eliminate the oscillation mode ambiguity and save the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5638 – 5650
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714874
Publisher: IEEE

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A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation

A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation 150 150
Author(s): Xuansheng Ji, Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Abstract:

This article presents a coherent polar phase-tracking receiver (PT-RX) for low-power Internet-of-Things(IoT) applications that supports Gaussian frequency-shift keying (GFSK), quadrature amplitude modulation (QAM), and amplitude phase shift keying (APSK). Existing single-path closed-loop receivers achieve low power but suffer from a fundamental tradeoff between loop stability and adjacent channel rejection (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5370 – 5382
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712802
Publisher: IEEE

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A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

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