IEEE Journal of Solid-State Circuits

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A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm 150 150
Author(s): Brian Zimmer, Stephen G. Tell, C. Thomas Gray

Abstract:

This work presents a self-timed die-to-die link that serializes four data bits per pin for 2.5-D, or 3-D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of one cycle, energy efficiency of 77 fJ/b, and bandwidth density of 44…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658215
Publisher: IEEE

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A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator

A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator 150 150
Author(s): Hyeonjun Nam, Hyogyoung An, Changmin An, Sungjin Kim, Heein Yoon

Abstract:

This article presents an injection-locked clock multiplier (ILCM) achieving the low-reference spur (spur ${}_{mathrm {REF}}$ ) with minimal overhead of a calibrator. To remove the dominant sources of frequency error, which are frequency drift ( $f_{mathrm {DF}}$ ), phase offset ( $varPhi _{mathrm {OS}}$ ), and injection-induced phase error ( $varPhi _{mathrm {INJ}}$ ), the ILCM …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650135
Publisher: IEEE

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A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms

A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms 150 150
Author(s): Javier Diaz-Fortuny, Erik Bury, Robin Degraeve, Ben Kaczer

Abstract:

Ring-oscillator (RO) circuits have historically been used to characterize the performance of CMOS technologies, as they can easily expose both process variability and aging through a straightforward circuit structure. ROs are widely employed to study degradation mechanisms such as bias temperature instability (BTI) and hot carrier degradation (HCD), which progressively …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653472
Publisher: IEEE

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A 4.21-to-15.18 GHz Magnetically Reconfigurable and Fully Symmetrical Quad-Core Quad-Mode VCO

A 4.21-to-15.18 GHz Magnetically Reconfigurable and Fully Symmetrical Quad-Core Quad-Mode VCO 150 150
Author(s): Shijin Huang, Pei Qin, Xiang Yi, Haoshen Zhu, Liang Wu, Quan Xue

Abstract:

This work proposes a wideband low phase noise (PN) quad-core quad-mode voltage-controlled oscillator (VCO) which features magnetically reconfigurable (MR) technique and fully symmetrical architecture. The MR technique, realized through a transformer-based tank integrating an embedded switched inductor, leverages varying core excitation currents to achieve four distinct equivalent inductances, thereby enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657757
Publisher: IEEE

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Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System

Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System 150 150
Author(s): Hiroshi Fuketa, Ippei Akita, Hanpei Koike, Takahiro Mori

Abstract:

Cryogenic CMOS (cryo-CMOS) quantum bit (qubit) control circuits are expected to overcome the interconnect complexity problem in large-scale quantum computers. However, since each qubit has a unique frequency for control, many power-hungry oscillators are needed to generate the frequencies at the cryogenic temperature stage of a refrigerator. In this article, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658602
Publisher: IEEE

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ANP-O: A 67 μW/Channel, 0.13 nW/Synapse/Bit Nose-on-a-Chip for Noninvasive Diagnosis of Diseases With On-Chip Incremental Learning

ANP-O: A 67 μW/Channel, 0.13 nW/Synapse/Bit Nose-on-a-Chip for Noninvasive Diagnosis of Diseases With On-Chip Incremental Learning 150 150
Author(s): Dexuan Huo, Yu-Hsien Lin, P. K. Shihabudeen, Jilin Zhang, Chi-Rong Chou, Zhihua Wang, Kea-Tiong Tang, Hong Chen

Abstract:

Portable electronic nose (E-nose) is considered as an innovative diagnostic tool designed to detect pathological changes in the body by analyzing a patient’s exhaled breath. However, the accuracy of E-nose is affected greatly by environmental factors and the use of different devices in various settings, such as hospitals, health …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656214
Publisher: IEEE

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A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing

A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing 150 150
Author(s): Haochen Zhang, Wei-Han Yu, Zhongyu Zhao, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui P. Martins, Pui-In Mak

Abstract:

This article presents an ultralow-power (ULP), battery-free intelligent silicon platform for distributed, multimodal sensing with adaptive, event-driven computing in edge devices. The proposed silicon platform incorporates hardware–software co-design in the implementation. At the algorithm level, a lightweight forward-forward (Lite-FF) algorithm is proposed to enable: 1) distributed model training with low-bitwidth …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656981
Publisher: IEEE

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A 52Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS

A 52Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS 150 150
Author(s): Chun Wang, Olivia Angel Yong, Hans Herdian, Wenqian Wang, Abanob Shehata, Carrel da Gomez, Chenxin Liu, Yudai Yamazaki, Kazuaki Kunihiro, Hiroyuki Sakai, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a 300-GHz-band amplifier-last outphasing phased-array transmitter with path mismatch calibration in a 65-nm CMOS technology. Calibration is essential for mitigating impairments in outphasing systems used for wideband communication. The transmitter integrates two independent sub-THz LO generation chains to calibrate the phase mismatch between two paths and configure …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657367
Publisher: IEEE

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Theoretical Analysis and Design of a 22–44-GHz Quasi-Balanced Doherty Power Amplifier With Enhanced Wideband PAE Performance and 3:1 VSWR Tolerance in 28-nm FD-SOI CMOS

Theoretical Analysis and Design of a 22–44-GHz Quasi-Balanced Doherty Power Amplifier With Enhanced Wideband PAE Performance and 3:1 VSWR Tolerance in 28-nm FD-SOI CMOS 150 150
Author(s): Gwennaël Diverrez, Eric Kerhervé, Magali De Matos, Andreia Cathelin

Abstract:

This article presents a broadband 5G power amplifier (PA) robust to voltage standing wave ratio (VSWR) variations and featuring high efficiency up to deep power back-off (PBO) in 28-nm FD-SOI CMOS technology. The proposed architecture, based on a quasi-balanced structure and an inductive load, offers an alternative to the conventional …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656824
Publisher: IEEE

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