IEEE Journal of Solid-State Circuits

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ANP-O: A 67 μW/Channel, 0.13 nW/Synapse/Bit Nose-on-a-Chip for Noninvasive Diagnosis of Diseases With On-Chip Incremental Learning

ANP-O: A 67 μW/Channel, 0.13 nW/Synapse/Bit Nose-on-a-Chip for Noninvasive Diagnosis of Diseases With On-Chip Incremental Learning 150 150
Author(s): Dexuan Huo, Yu-Hsien Lin, P. K. Shihabudeen, Jilin Zhang, Chi-Rong Chou, Zhihua Wang, Kea-Tiong Tang, Hong Chen

Abstract:

Portable electronic nose (E-nose) is considered as an innovative diagnostic tool designed to detect pathological changes in the body by analyzing a patient’s exhaled breath. However, the accuracy of E-nose is affected greatly by environmental factors and the use of different devices in various settings, such as hospitals, health …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656214
Publisher: IEEE

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A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing

A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing 150 150
Author(s): Haochen Zhang, Wei-Han Yu, Zhongyu Zhao, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui P. Martins, Pui-In Mak

Abstract:

This article presents an ultralow-power (ULP), battery-free intelligent silicon platform for distributed, multimodal sensing with adaptive, event-driven computing in edge devices. The proposed silicon platform incorporates hardware–software co-design in the implementation. At the algorithm level, a lightweight forward-forward (Lite-FF) algorithm is proposed to enable: 1) distributed model training with low-bitwidth …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656981
Publisher: IEEE

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A 52Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS

A 52Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS 150 150
Author(s): Chun Wang, Olivia Angel Yong, Hans Herdian, Wenqian Wang, Abanob Shehata, Carrel da Gomez, Chenxin Liu, Yudai Yamazaki, Kazuaki Kunihiro, Hiroyuki Sakai, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a 300-GHz-band amplifier-last outphasing phased-array transmitter with path mismatch calibration in a 65-nm CMOS technology. Calibration is essential for mitigating impairments in outphasing systems used for wideband communication. The transmitter integrates two independent sub-THz LO generation chains to calibrate the phase mismatch between two paths and configure …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657367
Publisher: IEEE

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Theoretical Analysis and Design of a 22–44-GHz Quasi-Balanced Doherty Power Amplifier With Enhanced Wideband PAE Performance and 3:1 VSWR Tolerance in 28-nm FD-SOI CMOS

Theoretical Analysis and Design of a 22–44-GHz Quasi-Balanced Doherty Power Amplifier With Enhanced Wideband PAE Performance and 3:1 VSWR Tolerance in 28-nm FD-SOI CMOS 150 150
Author(s): Gwennaël Diverrez, Eric Kerhervé, Magali De Matos, Andreia Cathelin

Abstract:

This article presents a broadband 5G power amplifier (PA) robust to voltage standing wave ratio (VSWR) variations and featuring high efficiency up to deep power back-off (PBO) in 28-nm FD-SOI CMOS technology. The proposed architecture, based on a quasi-balanced structure and an inductive load, offers an alternative to the conventional …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656824
Publisher: IEEE

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A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion

A 54- $\\mu$ W Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion 150 150
Author(s): Yudhajit Ray, Archisman Ghosh, Sarthak Antal, Shreyas Sen

Abstract:

This article presents a state-of-the-art design-agnostic clock, voltage, and electromagnetic pulse (EMP)-based fault-injection attack (FIA) detector. The efficient conversion of time-to-voltage information by integrating amplifiers transforms the time anomaly into the voltage domain, enabling its detection at a lower power consumption. The clock-glitch detector design consumes only $53~\mu $ W …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655593
Publisher: IEEE

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Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers

Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers 150 150
Author(s): Vinay Chenna, Hossein Hashemi

Abstract:

A topology optimization methodology is presented for the design of multistage, multipath, linear and nonlinear millimeter-wave (mm-Wave) power amplifiers (PAs). Optimization algorithms autonomously generate complete multilayered PA core layouts, including actives and passives, with minimal human intervention in just a few days. Experimental results from fabricated linear and nonlinear W-band …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656334
Publisher: IEEE

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A High-Power Wideband Sub-THz Power Amplifier With Asymmetric Slotline-Based Series–Parallel Combiner in 130-nm SiGe BiCMOS Technology

A High-Power Wideband Sub-THz Power Amplifier With Asymmetric Slotline-Based Series–Parallel Combiner in 130-nm SiGe BiCMOS Technology 150 150
Author(s): Gunwoo Park, Hyunjoon Kim, Sanggeun Jeon

Abstract:

This article presents a high-power, wideband sub-terahertz power amplifier (PA) implemented in a 130-nm SiGe BiCMOS technology. The PA features a novel asymmetric slotline-based series–parallel combiner (ASSPC) for output power combining. The ASSPC provides both low-loss, wideband combining and efficient admittance matching for four differential cascode PA unit cells, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656477
Publisher: IEEE

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SiWB: A 28-nm 800-MHz 4.2-to-14.2-Gb/s/W Configurable Multi-Core Architecture for White-Box Block Cipher With Area-Efficient Random Linear Transformation and Load-Aware Inter-Core Scheduling

SiWB: A 28-nm 800-MHz 4.2-to-14.2-Gb/s/W Configurable Multi-Core Architecture for White-Box Block Cipher With Area-Efficient Random Linear Transformation and Load-Aware Inter-Core Scheduling 150 150
Author(s): Xiangren Chen, Bohan Yang, Wenping Zhu, Hanning Wang, Jinjiang Yang, Min Zhu, Aoyang Zhang, Leibo Liu

Abstract:

White-box cryptography (WBC) seeks to protect secret keys (SKs) even under the white-box security model that features adversaries having full control of the execution environment. Due to the ever-growing demand for content protection under security-critical scenarios, the recent progress on WBC has been nothing short of spectacular. However, the security-prioritized …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3649035
Publisher: IEEE

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A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks

A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks 150 150
Author(s): Weizeng Li, Linfang Wang, Zhidao Zhou, Zhi Li, Wang Ye, Junyu Zhu, Junzhe Shen, Bohan Wang, Hanghang Gao, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Qi Liu, Chunmeng Dou, Yang Chai, Ming Liu

Abstract:

Designing computing-in-memory (CIM) chips with synaptic plasticity can potentially support energy-efficient on-chip learning in edge devices for rapid local task adaptation. Its silicon implementation is challenging as it requires hybridizing nonvolatile and volatile memory (VM) and customized computational operations. In this work, we propose a plastic CIM (P-CIM) macro featuring: 1) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652940
Publisher: IEEE

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