IEEE Journal of Solid-State Circuits

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing 150 150

Abstract:

Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (…

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A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators 150 150

Abstract:

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC …

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Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode

Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode 150 150

Abstract:

Body-coupled powering (BCP) and body-coupled communication (BCC) utilize the human body channel as the wireless transmission medium, which shows less path loss around the body area. However, integrating both BCP and BCC requires multiple electrodes or alternating the uplink and downlink in the time domain, due to signal interferences and …

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking 150 150

Abstract:

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. …

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New Associate Editor

New Associate Editor 150 150

Abstract:

It is with great pleasure that I welcome Prof. Jie Gu to the Editorial Board of the IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Gu is an expert in high-performance and energy-efficient digital circuits, including domain-specific accelerators.

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New Associate Editor

New Associate Editor 150 150

Abstract:

It is with great pleasure that I welcome Prof. Priyanka Raina to the Editorial Board of the IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Raina is an expert in architectures and circuits for domainspecific accelerators.

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A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques

A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques 150 150

Abstract:

The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while …

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EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning

EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning 150 150

Abstract:

Deep neural networks (DNNs) have recently gained significant prominence in various real-world applications such as image recognition, natural language processing, and autonomous vehicles. However, due to their black-box nature in system, the underlying mechanisms of DNNs behind the inference results remain opaque to users. In order to address this challenge, …

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8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter

8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter 150 150

Abstract:

We demonstrate a 3-D heterogeneously integrated dense wavelength-division multiplexing (DWDM) silicon-photonic transmitter simultaneously modulating eight 200-GHz spaced wavelengths at 50 Gbps/ $\lambda $ each, to deliver an aggregate per-fiber bandwidth of 400 Gbps. All necessary $O$ -band optical components are fully integrated on the photonic integrated circuit (PIC), including an eight-wavelength laser array, …

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