IEEE Journal of Solid-State Circuits

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A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks

A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks 150 150
Author(s): Weizeng Li, Linfang Wang, Zhidao Zhou, Zhi Li, Wang Ye, Junyu Zhu, Junzhe Shen, Bohan Wang, Hanghang Gao, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Qi Liu, Chunmeng Dou, Yang Chai, Ming Liu

Abstract:

Designing computing-in-memory (CIM) chips with synaptic plasticity can potentially support energy-efficient on-chip learning in edge devices for rapid local task adaptation. Its silicon implementation is challenging as it requires hybridizing nonvolatile and volatile memory (VM) and customized computational operations. In this work, we propose a plastic CIM (P-CIM) macro featuring: 1) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652940
Publisher: IEEE

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A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing

A 19.4-fsRMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing 150 150
Author(s): Jinhai Xiao, Yong Chen, Ningyi Zhang, Xiaolong Liu, Rui Liu, Junao Zhu, Chenghao Zhang, Peng Luo, Maliang Liu, Yintang Yang, Xiaohua Ma, Yue Hao

Abstract:

Cryogenic fractional- $N$ phase-locked loops (PLLs) are essential for large-scale superconducting quantum computing, and serve as integrated pump sources for Josephson parametric amplifiers. These PLLs enable high-fidelity qubit readout while reducing the thermal load and wiring complexity associated with room-temperature generators. However, the cryogenic pump sources developed thus far were …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653994
Publisher: IEEE

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A SPAD Flash LiDAR Sensor With Push-Pull Analog Counter Achieving a 0.12% Depth Precision at a 70 m Depth Range

A SPAD Flash LiDAR Sensor With Push-Pull Analog Counter Achieving a 0.12% Depth Precision at a 70 m Depth Range 150 150
Author(s): Dongseok Cho, Byungchoul Park, Hyun-Seung Choi, Myung-Jae Lee, Youngcheol Chae

Abstract:

This article presents a $64 {times } 64$ SPAD flash LiDAR sensor that achieves a depth precision of 0.12% across a 70 m depth range. The sensor is built on a time-gated single-photon counting (TGSPC) architecture that integrates a back-side illuminated (BSI) single-photon avalanche diode (SPAD), a pulse-shaping circuit, a push-pull analog pulse counter, and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655000
Publisher: IEEE

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25-Gb/s 850-nm Monolithic Optical Receiver With a Si APD Bias Controller Using Histogram Monitoring

25-Gb/s 850-nm Monolithic Optical Receiver With a Si APD Bias Controller Using Histogram Monitoring 150 150
Author(s): Jae-Ho Lee, Seung-Jae Yang, Myung-Jae Lee, Woo-Young Choi

Abstract:

We demonstrate a 25-Gb/s 850-nm monolithic optical receiver containing a Si avalanche photodetector (APD) realized in standard 28-nm complementary metaloxidesemiconductor (CMOS) technology without any design rule violations or process modifications. The optical receiver includes the Si APD bias controller that provides the Si APD reverse bias voltage by regulating …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3654962
Publisher: IEEE

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Dual-Mode Inverter-Based Write Termination Scheme for Energy- and Area-Efficient Write Operation in 28-nm 1T1MTJ STT-MRAM

Dual-Mode Inverter-Based Write Termination Scheme for Energy- and Area-Efficient Write Operation in 28-nm 1T1MTJ STT-MRAM 150 150
Author(s): Do-Yoon Lim, Donghan Ko, Sekeon Kim, Sunjong Park, Wangyu Lee, Taegeon Min, Jihoo Moon, Seong-Ook Jung

Abstract:

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising non-volatile memory, but its write operation requires a large static current, leading to high write power. Resistance-monitoring write termination (RM-WT) schemes were introduced to reduce write power, but they suffer from several limitations: 1) the sensing circuit (SC) used in previous …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3654895
Publisher: IEEE

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A Compact, Wideband Complex Cascode Power Amplifier With LC Neutralization for VSWR-Resilient Operation in High-Density Phased Arrays

A Compact, Wideband Complex Cascode Power Amplifier With LC Neutralization for VSWR-Resilient Operation in High-Density Phased Arrays 150 150
Author(s): Mohamed Eleraky, Tzu-Yuan Huang, Hua Wang

Abstract:

This article proposes a design methodology for achieving intrinsic performance resilience in power amplifiers (PAs) against antenna impedance variations inherent to modern phased-array systems through the improvement of the PA output matching ( $S!_{22}$ ). This goal, however, presents a challenge for conventional cascode PAs due to their inherently high output impedance …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3654669
Publisher: IEEE

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A 136.6-dB-DR 174.3-dB-FoMS Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop

A 136.6-dB-DR 174.3-dB-FoMS Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop 150 150
Author(s): Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Yeonjae Shin, Jeongyoon Wie, Seungyeob Baik, Hongki Kang, Minyoung Song, Jong-Hyeok Yoon, Junghyup Lee

Abstract:

This article presents a high-resolution, wide dynamic-range (DR) current-to-digital converter (IDC) capable of directly digitizing a broad range of bio-current signals. To achieve high resolution, the IDC uses a second-order continuous-time delta–sigma modulator (CT-DSM) architecture with a low-noise current-recycling operational amplifier (op-amp) and a highly linear pseudo-differential voltage-controlled oscillator (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653442
Publisher: IEEE

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0.13 K NETD D-Band CMOS Passive Imager With Noise Suppression Analysis

0.13 K NETD D-Band CMOS Passive Imager With Noise Suppression Analysis 150 150
Author(s): Zahra Mohseni, Sajjad Sabbaghi, Hai Yu, Peixin Han, Yuhao Yuan, Qun Jane Gu

Abstract:

This article presents a new system design and in-depth analysis of a wideband, low-power passive imaging receiver based on a Dicke-switch architecture, implemented in 28 nm CMOS technology. The proposed structure employs a three-coil gm-boosting technique for the low-noise amplifier (LNA). This approach reduces the LNA’s noise figure (NF) and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3646943
Publisher: IEEE

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A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT

A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT 150 150
Author(s): Jiahao Shi, Xuchu Mu, Qiaobo Ma, Yang Jiang, Rui P. Martins, Pui-In Mak

Abstract:

This article presents a power- and area-efficient switched-capacitor (SC) ac–dc converter in low-voltage (LV) CMOS for mains-powered Internet of Things (IoT) applications. The proposed converter adopts a single-stage series-capacitor architecture with fine-grained pre-rectification regulation, eliminating the need for intermediate high-voltage (HV) dc capacitors or HV dc–dc stages, thereby …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650592
Publisher: IEEE

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