IEEE Journal of Solid-State Circuits

A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR

A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR 150 150

Abstract:

This article presents a low-power (LP), compact, wideband (WB) low-noise transconductance amplifier (LNTA)-first receiver (RX) designed for software-defined radios (SDRs). It comprises the LNTA, frequency divider, mixer, and trans-impedance amplifier (TIA). The LNTA utilizes a common gate (CG)-common source (CS) structure without on-chip inductors and incorporates gm-boosting and …

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A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency

A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency 150 150

Abstract:

This article presents a compact 24–30-GHz phased array transceiver (TRX) front end (FE) with high transmitter (TX) power efficiency and low receiver (RX) noise figure (NF) in a 130-nm bipolar CMOS (BiCMOS) technology supporting different 5th generation mobile network (5G) frequency range 2 (FR2) bands (n257, n258, and n261). We introduce …

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A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET

A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET 150 150

Abstract:

High-speed radiation-hardened frequency synthesizers are a key block in spaceborne communications systems. This article presents a 15–22-GHz radiation-hardened phase-locked loop (PLL) designed in a 22-nm FinFET process with hardening techniques for single-event upset (SEU) and total ionizing dose (TID) implemented in all key PLL blocks. Electrical performance tradeoffs arising from …

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A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis

A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis 150 150

Abstract:

BSTcontrol As neural network (NN) training cost red has been growing exponentially over the past decade, developing high-speed and energy-efficient training methods has become an urgent task. Fine-grained mixed-precision low-bit training is the most promising way for high-efficiency training, but it needs dedicated processor designs to overcome the overhead in …

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A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications

A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications 150 150

Abstract:

This article proposes a hybrid boost converter that eliminates the right-half-plane (RHP) zero. The proposed converter can be designed with a broad bandwidth up to a tenth of the switching frequency, such that the converter can attain fast transient response as a buck converter. Besides, it features a left-half-plane zero …

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Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits 150 150

Abstract:

This Special Issue of IEEE Journal of Solid-State Circuits highlights some of the outstanding circuit papers presented at the Symposium on VLSI Technology and Circuits. The Symposium was held in person, June 11–16, 2023, in Kyoto, Japan.

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Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting”

Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting” 150 150

Abstract:

In the above article [1], page 2605, the changes in Table II are as follows.

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A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces 150 150

Abstract:

The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to …

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