IEEE Journal of Solid-State Circuits

A Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception

A Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception 150 150

Abstract:

This work presents a programmable processor for both neural-network (NN)-based inference and localization in micro-robotic visual perception (VP). While specialized accelerators for the two applications demonstrate substantial energy efficiency and throughput gains, the built-in system with separate cores suffers from a mismatch across diverse robotic tasks, making it difficult …

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Cygnus: A Heterogeneous Octa-Core RISC-V Vector Processor for Digital Signal Processing Applications

Cygnus: A Heterogeneous Octa-Core RISC-V Vector Processor for Digital Signal Processing Applications 150 150

Abstract:

We introduce Cygnus, an energy-efficient octa-core RISC-V vector processor, compliant with the RISC-V vector extension (RVV) 1.0 specification, specifically designed for digital signal processing (DSP) and robotics applications. This system-on-chip (SoC) features dynamic instruction scheduling with short-vector lengths at the vector core level and employs a big/little architecture with tightly …

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A LEGO-Like Easy-Stacking SC Boost Converter

A LEGO-Like Easy-Stacking SC Boost Converter 150 150

Abstract:

This work presents an ultra-lightweight and small total PCB volume LEGO-like easy-stacking switched-capacitor (ESSC) step-up DC–DC converter with all input-voltage-stress-only devices for micro-actuator drivers. The proposed converter can achieve a very high-voltage conversion ratio (VCR) by multi-basic-cell stacking (BCS) with stacked power stages, level shifters (LSs), and drivers. The …

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Gain-Boosted N-Path Receiver With Harmonic Suppression and Scalable Clock Bootstrapping

Gain-Boosted N-Path Receiver With Harmonic Suppression and Scalable Clock Bootstrapping 150 150

Abstract:

This work presents a gain-boosted N-path receiver resilient to harmonic blockers by embedding harmonic-reset switching in the feedback path. A three-stage pipeline mixer is used for downconversion, enhancing conversion gain and extending third- and fifth-order harmonic rejection (HR). To reduce power consumption and ensure reliable operation at a 0.6-V supply, …

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A 71–86-GHz 1024-QAM Direct-Carrier Phase-Modulating Transmitter With Digital-to-Phase Converter and Constant-Envelope Phasor Combiner

A 71–86-GHz 1024-QAM Direct-Carrier Phase-Modulating Transmitter With Digital-to-Phase Converter and Constant-Envelope Phasor Combiner 150 150

Abstract:

This article presents a 71–86-GHz 1024-QAM direct-carrier phase-modulating transmitter (DCPM-TX) that synthesizes high-order QAM symbols using phase modulation only. The proposed approach employs dual 9-bit digital-to-phase converters (DTPCs) and a constant-envelope phasor combiner. Each DTPC uses coarse/fine-segmented digitally controlled switched-capacitor transmission lines (SCTLs) (true-time-delay operation) plus a sign mixer, …

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A 12-bit 1-GS/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation

A 12-bit 1-GS/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation 150 150

Abstract:

A 12-bit 1-GS/s three-stage pipelined analog-to-digital converter (ADC) employing an analog compensation technique to enhance residue amplifier (RA) gain linearity is presented. The proposed residue-dependent integration time compensation (RITC) technique mitigates the compressing nonlinearity in an RA by scaling the integration time for large RA input signals. This technique …

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A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging

A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging 150 150

Abstract:

This article presents a high-accuracy, low-drift 16MHz RC frequency reference implemented in a standard 180 nm CMOS process. It consists of a frequency-locked loop (FLL), which locks the output frequency of a digitally controlled oscillator (DCO) to the time constant of a Wien Bridge (WB) filter. A PNP-based temperature sensor (TS) …

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A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM

A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM 150 150

Abstract:

This article presents a noise-shaping successive approximation register (NS-SAR)-based direct-digitizing electrophysiological (ExG) sensing frontend (SFE) fabricated in a standard 180-nm CMOS process. To address the challenges of large motion artifacts and high electrode–tissue impedance (ETI), we propose three key innovations in our proposed SFE that enable accurate ExG …

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A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load

A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load 150 150

Abstract:

On-cell touch flexible organic light-emitting diode (OLED) displays face significant display noise (D-noise) challenges due to large parasitic capacitance ( $C_{P}$ ). To address the limitations of conventional methods, this article proposes improved common-current subtraction (CCS), incorporating common-voltage subtraction (CVS) and common-charge subtraction (CQS) techniques. CVS enhances signal-to-noise ratio (SNR) by …

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