SSCS December Technical Webinar: How Close Should Compute and Memory Be?

11 December @ 11:00 am EST
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Abstract: Compute-in-memory (CIM) and processing-near-memory (PNM) have emerged as promising approaches to overcome the limitations of architectures that separate processing from memory. While this bottleneck is often attributed to von Neumann’s design, such critiques overlook its historical significance: the separation of logic and memory enabled the decoupling of software from hardware, laying the foundation for general-purpose computing. In this talk, we explore three key considerations in response to the question: How close should compute and memory be? First, memory and logic technologies follow distinct optimization paths. While integrating logic with memory may reduce local data movement, it may also compromise memory density, leading to more off-chip access and lower overall efficiency. Maintaining a degree of separation enables each technology to optimize its strengths, which can lead to greater overall efficiency. Second, tightly integrating compute and memory may constrain logic complexity due to limited area within the memory core, reducing architectural adaptability. As machine learning models continue to evolve, rigid architectures may reduce flexibility, thus hindering their adoption. Architectural flexibility is therefore essential to support diverse and rapidly advancing AI models. Third, current systems and applications are deeply rooted in established architectures, with substantial investment in software infrastructure and development platforms. Meaningful progress toward new paradigms requires coordinated efforts across hardware, software, and domain expertise. We hope to raise awareness of these three areas as researchers continue to innovate toward addressing the energy challenges posed by artificial intelligence.

 Register here: https://ieee.webex.com/weblink/register/ra9927b025cf323410950703e7b6f2208

Bio: Shih-Lien Lu is a veteran in semiconductor and computer architecture, with extensive experience in both academia and industry. He is currently a Professor in the School of Electrical Engineering and Computer Science at Washington State University, Everett. He previously taught at Warner Pacific University (2021–2023) and Oregon State University (1991–2001). His industry experience includes serving as Chief Solutions Officer at PieceMakers Technology (2021–2023); Director of R&D at Taiwan Semiconductor Manufacturing Company (TSMC) (2016–2021); Director of the Memory Architecture Lab at Intel Labs; and Design Manager at the MOSIS Project, USC/ISI. His research interests span computer architecture, memory circuits and technologies, and hardware security. An IEEE Fellow, Shih-Lien received his B.S. in Electrical Engineering and Computer Science from UC Berkeley and both his M.S. and Ph.D. in Computer Science and Engineering from UCLA.

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