Abstract: Advancements in technology scaling have ushered in larger systems boasting enhanced functionality, increased operational speed, and expanded data bandwidth. However, these benefits come with more demanding clocking requirements, including extended distribution distances and heightened timing precision. Furthermore, technology scaling has rendered traditional analog design challenging. Wider PVT variations necessitate intensive calibration efforts, and increased integration levels call for resilience against external noise sources. Moreover, the fact that reference frequency and loop bandwidth do not scale at the same rate as technology leads to prohibitive costs for oversized loop filters. While pure analog implementations offer intuitive operation and elegant analysis, clocking circuits incorporating digital elements offer effective solutions to these challenges.
This presentation will cover how digital circuits can enhance clock generation and distribution through techniques like calibration and signal processing. Beginning with well-established methods that harness the mixed-signal nature of PLLs, such as delta-sigma modulation for the MDD in fractional-N PLLs, the presentation will shift toward digital-intensive architectures. It will focus on techniques that leverage digital implementations for error detection and enhance timing accuracy through either analog or digital correction. State-of-the-art designs featuring runtime calibration and power noise cancellation for clock generation and distribution will also be introduced. This talk will conclude with insights into future challenges and trends.
Presenter Bio: Ping-Hsuan Hsieh received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, Los Angeles, CA, in 2004 and 2009, respectively. From 2009 to 2011, she was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2011 she joined the Electrical Engineering Department of National Tsing Hua University, Hsinchu, Taiwan, where she is currently an Associate Professor. Her research interests focus on mixed-signal integrated circuit designs for high-speed electrical data communications, clocking and synchronization systems, and energy-harvesting systems.
Prof. Hsieh is a TPC Member of ISSCC, an Associate Editor of TCAS-I, and an SSCS AdCom Member-at-Large. She also served as a TPC member for A-SSCC and CICC, an Associate Editor for OJCAS, SSC-L, a Guest Editor for JSSC, and an IEEE SSCS Distinguished Lecturer (2023-2024).