IEEE Solid-State Circuits Letters

  • No Comments

A 58.9—73.7-GHz Quadrature Dual-Core Class-F3,5 Oscillator with Tail-Assisted Implicit Quintupling

A 58.9—73.7-GHz Quadrature Dual-Core Class-F3,5 Oscillator with Tail-Assisted Implicit Quintupling 150 150
Author(s): Yevhenii Mormul, Patchara Sawakewang, Sayan Kumar, Chawin Khongprasongiri, Teerachot Siriburanon, Robert Bogdan Staszewski

Abstract:

We introduce a new class-F3,5 oscillator topology that enables quadrature operation by duplicating a conventional class-F3 oscillator core and electro-magnetically coupling the two cores through a pair of additional coils feeding source terminals of the gm transistors. The coupling network enhances the 5th-harmonic component, enabling efficient extraction and quadrature operation …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3699799
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An IEEE802.15.4a/z/ab compatible IR-UWB 2TRX with full-duplex radar sensing and aliasing suppressing semi-synchronous TX

An IEEE802.15.4a/z/ab compatible IR-UWB 2TRX with full-duplex radar sensing and aliasing suppressing semi-synchronous TX 150 150
Author(s): Anoop Narayan Bhat, Erwin Allebes, Elbert Bechthum, Zule Xu, Stan Van Der Ven, Mohieddine El Soussi, Johan Van Den Heuvel, Paul Van Zeijl, Paul Mateman, Murat Eskiyerli, Stefano Traferro, Amirashkan Farsaei, Evgenii Tiurin, Sahan Gamage, Pepijn Boer, Igor Petrov, Jochem Govers, Huib Visser, Martijn Hijdra, Sharada Prasad Shantharam, Ivo Marques, Gururaja Kasanadi Ramachandra, Kaijie Ding, Ran Li, Aasish Boora, Peter Vis, Mario Konijnenburg, Arjan Breeschoten, Peng Zhang, Yao-Hong Liu, Christian Bachmann

Abstract:

This letter presents an 802.15.4ab/a/z compatible IR-UWB 2TRX highlighting a full-duplex-based radar, a semi-synchronous TX and TRX’s digital baseband. A capacitive tuning technique proposed in the electrical balance duplexer (EBD)-based duplex RF front-end (RF-FE) improves TX-antenna insertion loss by 1.4dB and the sensitivity of TX-RX isolation …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697493
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only …

Published in: IEEE Solid-State Circuits Letters
Page(s): 178 – 181
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The …

Published in: IEEE Solid-State Circuits Letters
Page(s): 186 – 189
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors

An Inductive-Load-Modulated Multiband Phase Shifter With <0.38°/0.12-dB RMS Errors 150 150
Author(s): Xinyi Wu, Chenxu Zhao, Hui Chen, Xun Bao, Yaolong Hu, Aoyang Zhang, Leibo Liu

Abstract:

This letter presents a compact, multiband reflection-type phase shifter (RTPS) implemented in 65-nm CMOS that overcomes the narrowband limitations of conventional passive loads. The proposed design utilizes an inductive-load modulation. By injecting a secondary signal to actively manipulate the magnetic flux, the equivalent inductance is boosted to enable operation across …

Published in: IEEE Solid-State Circuits Letters
Page(s): 170 – 173
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3694867
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS

A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS 150 150
Author(s): Wei-Yu Lin, Nikhil Jain, Jun-Chau Chien

Abstract:

Implementing oscillators with harmonic engineering beyond 60-GHz poses significant challenges due to the need for small inductors resonating beyond 120 GHz. To address this issue, this work presents a 60-GHz standing-wave oscillator (SWO) with both second- and third-harmonic boosting for phase noise reduction. A triple-line resonator is proposed to sustain both …

Published in: IEEE Solid-State Circuits Letters
Page(s): 158 – 161
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3693153
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback

Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback 150 150
Author(s): Ehsan Semsar Parapari, Marco Bennati, Michele Biondi, Marco Crescentini, Federico Thei

Abstract:

This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure p-n junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback …

Published in: IEEE Solid-State Circuits Letters
Page(s): 162 – 165
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692971
Publisher: IEEE

View on IEEE Xplore

Search this website