IEEE Solid-State Circuits Letters

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A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends

A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends 150 150
Author(s): S. Sarah Feng, Fuzhan Chen, H. Bruce Bao, R. Matthew Ma, Kangping Zhong, P. T. Alan Lau, C. Patrick Yue

Abstract:

This letter presents a broadband, high-optical modulation amplitude (OMA) GaN-based 1-to-N VCSEL driver implemented in a 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 242 – 245
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720689
Publisher: IEEE

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miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator 150 150
Author(s): Krishna Sai Tarun Ramapragada, Utsav Banerjee

Abstract:

We present the first ASIC demonstration of SQIsign, an isogeny-based National Institute of Standards and Technology (NIST)-candidate post-quantum digital signature scheme. Our optimized Montgomery modular multiplier circuit design enables $2\times $ speedup and energy savings, while an efficient memory organization provides a 31% area savings. We implement SQIsign-1D-Uncompressed signature verification …

Published in: IEEE Solid-State Circuits Letters
Page(s): 238 – 241
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720807
Publisher: IEEE

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE

A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE 150 150
Author(s): Yao-Hung Tsai, Ming-Han Chuang, Shen-Iuan Liu

Abstract:

A resistor-less 7-bit source-series-termination (SST) digital-to-analog converter (DAC)-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of the 4:1 multiplexer due to the inter-symbol-interference (ISI), the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 226 – 229
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3722281
Publisher: IEEE

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A Sensing-Security Co-Design Based on Intrinsic Device Variations for Self-Authenticating Sensors

A Sensing-Security Co-Design Based on Intrinsic Device Variations for Self-Authenticating Sensors 150 150
Author(s): Ruochen Wang, Tetsuya Hirose, Jun Shiomi, Yoshihiro Midoh, Takuji Miki, Makoto Nagata, Noriyuki Miura

Abstract:

This article presents an extended analog signature framework (ASF) that realizes sensing-security co-design by embedding authentication directly within the sensor analog front-end. Building on prior work, the extended design addresses entropy stabilization and structural periodicity through refined selection and measurement-bound feedback. Intrinsic transistor-level mismatches are reused as resources for authenticating, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 246 – 249
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725256
Publisher: IEEE

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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

Published in: IEEE Solid-State Circuits Letters
Page(s): 250 – 253
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725284
Publisher: IEEE

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A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 150 150
Author(s): Lexie Drackley, Aman Gupta, David D. Wentzloff

Abstract:

This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3716852
Publisher: IEEE

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A Broadband Class-E Power Amplifier with Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS

A Broadband Class-E Power Amplifier with Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS 150 150
Author(s): Kai Yue, Yubing Li, Yujia Chen, Xiuping Li

Abstract:

This letter presents a compact Class-E power amplifier (PA) with broadband and enhanced harmonic suppression performance. The harmonic suppression susceptance compensation (HSSC) Class-E load network is proposed and analyzed to simultaneously achieve broadband fundamental matching and harmonic suppression. Despite its sixth-order LC complexity, the proposed HSSC Class-E load network is …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725042
Publisher: IEEE

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A CMOS LNA with an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications

A CMOS LNA with an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 150 150
Author(s): Yunfan Gao, Minghan Liu, Mengting Yan, Cristian Cassella, Miriam Leeser, Marvin Onabajo

Abstract:

This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct down-conversion mixing, which avoids a dedicated LO generator, coupler, or …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725828
Publisher: IEEE

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