IEEE Solid-State Circuits Letters

A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE

A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE 150 150

Abstract:

A resistor-less 7-bit source-series-termination (SST) digital-to-analog converter (DAC)-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of the 4:1 multiplexer due to the inter-symbol-interference (ISI), the …

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A Broadband Class-E Power Amplifier With Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS

A Broadband Class-E Power Amplifier With Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS 150 150

Abstract:

This letter presents a compact Class-E power amplifier (PA) with broadband and enhanced harmonic suppression performance. The harmonic suppression susceptance compensation (HSSC) Class-E load network is proposed and analyzed to simultaneously achieve broadband fundamental matching and harmonic suppression. Despite its sixth-order $LC$ complexity, the proposed HSSC Class-E load network is …

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A Sensing-Security Co-Design Based on Intrinsic Device Variations for Self-Authenticating Sensors

A Sensing-Security Co-Design Based on Intrinsic Device Variations for Self-Authenticating Sensors 150 150

Abstract:

This article presents an extended analog signature framework (ASF) that realizes sensing-security co-design by embedding authentication directly within the sensor analog front-end. Building on prior work, the extended design addresses entropy stabilization and structural periodicity through refined selection and measurement-bound feedback. Intrinsic transistor-level mismatches are reused as resources for authenticating, …

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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 150 150

Abstract:

This letter presents a fractional-N digital phase-locked loop (DPLL) employing a dynamic-threshold digital-to-time converter (DT-DTC). By dynamically adjusting the comparator threshold voltage, the proposed DT-DTC mitigates delay nonlinearity without digital predistortion (DPD). A quadrature-VCO (QVCO) generates quadrature phases for a multiphase clock generator (MPCG). The QVCO-based MPCG with skew calibration …

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A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 150 150

Abstract:

This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct downconversion mixing, which avoids a dedicated LO generator, coupler, or …

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A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure

A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure 150 150

Abstract:

The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this article proposes a global merged reference-based magnetic random access memory (MRAM) logic-in-memory (LIM) structure. The proposed structure generates operation-specific reference resistances by controlling the effective …

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A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C

A Delay-Compensated RC Oscillator With Constant Ramp Peak-Voltage Achieving 23 ppm/°C Temperature Coefficient from -40 to 100 °C 150 150

Abstract:

This letter presents a delay-compensated RC relaxation oscillator for enhanced frequency stability. The proposed architecture employs a peak-sampling circuit to detect the charging-capacitor peak voltage. A feedback loop composed of an error amplifier and compensation resistors adaptively raises the capacitor DC baseline to compensate for comparator-delay-induced frequency error, while phase-alternating …

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A 28nm Reconfigurable CAM for High-Utilization String Matching

A 28nm Reconfigurable CAM for High-Utilization String Matching 150 150

Abstract:

Content-addressable memory (CAM) is essential for data-intensive applications such as network packet classification, but conventional row-by-row architectures store one fixed-width rule per row, so variable-length rules must be padded to the row width, limiting the average array utilization to 53.1% for a representative uniform 1–16-byte rule-length distribution. This letter proposes a …

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A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs

A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs 150 150

Abstract:

Sub-sampling PLLs use a transconductor following the sampling phase detector. To reduce the loop-filter capacitor size, a small transconductance with polarity switching can drive a switched-capacitor loop filter; however, slow settling introduces uncertainty in the PLL parameters, and excess output noise directly contributes to PLL jitter. Realizing a small transconductance …

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