IEEE Solid-State Circuits Letters

  • No Comments

A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling

A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling 150 150
Author(s): Yevhenii Mormul, Patchara Sawakewang, Sayan Kumar, Chawin Khongprasongsiri, Teerachot Siriburanon, Robert Bogdan Staszewski

Abstract:

We introduce a new class-F3,5 oscillator topology that enables quadrature operation by duplicating a conventional class-F3 oscillator core and electromagnetically coupling the two cores through a pair of additional coils feeding source terminals of the $g_{m}$ transistors. The coupling network enhances the fifth-harmonic component, enabling efficient extraction and quadrature …

Published in: IEEE Solid-State Circuits Letters
Page(s): 198 – 201
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3699799
Publisher: IEEE

View on IEEE Xplore

  • No Comments

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator 150 150
Author(s): Krishna Sai Tarun Ramapragada, Utsav Banerjee

Abstract:

We present the first ASIC demonstration of SQIsign, an isogeny-based NIST-candidate post-quantum digital signature scheme. Our optimized Montgomery modular multiplier circuit design enables 2× speedup and energy savings, while efficient memory organization provides 31% area savings. We implement SQIsign-1D-Uncompressed signature verification in a small form factor with low power consumption suitable …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720807
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential PAM-3 transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard deviation of …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 0.68nJ/solution Inverse-Matrix-Vector Multiplication Solver with Decoupled Input Injection Scheme in 65nm CMOS

A 0.68nJ/solution Inverse-Matrix-Vector Multiplication Solver with Decoupled Input Injection Scheme in 65nm CMOS 150 150
Author(s): Hsiang-Chun Cheng, Mayank Palaria, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen

Abstract:

This paper presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717659
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 150 150
Author(s): Lexie Drackley, Aman Gupta, David D. Wentzloff

Abstract:

This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3716852
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX

An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX 150 150
Author(s): Anoop Narayan Bhat, Erwin Allebes, Elbert Bechthum, Zule Xu, Stan van der Ven, Mohieddine El Soussi, Johan van Den Heuvel, Paul van Zeijl, Paul Mateman, Murat Eskiyerli, Stefano Traferro, Amirashkan Farsaei, Evgenii Tiurin, Sahan Gamage, Pepijn Boer, Igor Petrov, Jochem Govers, Huib Visser, Martijn Hijdra, Sharada Prasad Shantharam, Ivo Marques, Gururaja Kasanadi Ramachandra, Kaijie Ding, Ran Li, Aasish Boora, Peter Vis, Mario Konijnenburg, Arjan Breeschoten, Peng Zhang, Yao-Hong Liu, Christian Bachmann

Abstract:

This letter presents an 802.15.4ab/a/z compatible IR-UWB 2TRX highlighting a full-duplex-based radar, a semisynchronous TX and TRX’s digital baseband. A capacitive tuning technique proposed in the electrical balance duplexer (EBD)-based duplex RF front-end (RF-FE) improves TX-antenna insertion loss by 1.4 dB and the sensitivity of TX–RX …

Published in: IEEE Solid-State Circuits Letters
Page(s): 190 – 193
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697493
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The …

Published in: IEEE Solid-State Circuits Letters
Page(s): 186 – 189
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C

A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 150 150
Author(s): Yiming Wang, Yihang Luan, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only …

Published in: IEEE Solid-State Circuits Letters
Page(s): 178 – 181
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697203
Publisher: IEEE

View on IEEE Xplore

Search this website