IEEE Solid-State Circuits Letters

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 150 150
Author(s): Lexie Drackley, Aman Gupta, David D. Wentzloff

Abstract:

This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3716852
Publisher: IEEE

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A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends

A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends 150 150
Author(s): S. Sarah Feng, Fuzhan Chen, H. Bruce Bao, R. Matthew Ma, Kangping Zhong, P. T. Alan Lau, C. Patrick Yue

Abstract:

This letter presents a broadband, high-optical modulation amplitude (OMA) GaN-based 1-to-N VCSEL driver implemented in a 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 242 – 245
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720689
Publisher: IEEE

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miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator 150 150
Author(s): Krishna Sai Tarun Ramapragada, Utsav Banerjee

Abstract:

We present the first ASIC demonstration of SQIsign, an isogeny-based National Institute of Standards and Technology (NIST)-candidate post-quantum digital signature scheme. Our optimized Montgomery modular multiplier circuit design enables $2\times $ speedup and energy savings, while an efficient memory organization provides a 31% area savings. We implement SQIsign-1D-Uncompressed signature verification …

Published in: IEEE Solid-State Circuits Letters
Page(s): 238 – 241
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720807
Publisher: IEEE

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A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential pulse-amplitude modulation (PAM-3) transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard …

Published in: IEEE Solid-State Circuits Letters
Page(s): 234 – 237
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

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A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS

A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS 150 150
Author(s): Hsiang-Chun Cheng, Mayank Palaria, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen

Abstract:

This letter presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 222 – 225
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717659
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 210 – 213
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

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A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications

A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications 150 150
Author(s): Bayartulga Ishdorj, Taehui Na

Abstract:

This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduces the overhead associated with replicated NV circuitry in conventional in situ NVFFs while enabling low power. By using only one NVFF per column and compact SCDFF-based volatile flip-flops (FFs), …

Published in: IEEE Solid-State Circuits Letters
Page(s): 206 – 209
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713204
Publisher: IEEE

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