IEEE Journal of Solid-State Circuits – Early Access

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An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS

An H-Band Continuous Broadband RF-Domain Quadrature Receiver Using a Harmonic-Enhanced LO Generator in 65-nm CMOS 150 150
Author(s): Weiping Wu, Xun Bao, Jingze Wang, Shi Chen, Shulan Chen, Yan Wang, Lei Zhang

Abstract:

This article presents an $H$ -band CMOS receiver chipset that covers a wide frequency range of 228–324 GHz, supporting the entire band of IEEE Std. 802.15.3d. The proposed receiver employs an RF-domain quadrature mixer-first architecture to alleviate the design burden of quadrature local oscillator (LO) signal generation in $H$ -band, which …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3697557
Publisher: IEEE

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GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection 150 150
Author(s): Mao Li, Sanu K. Mathew, Vivek De, Mingoo Seok

Abstract:

This article presents GUARD, a fully digital, variation-tolerant detector for clock and voltage glitch attacks, featuring an integrated on-demand protection mechanism. Fabricated in 28-nm CMOS, GUARD provides robust security for digital systems by monitoring the system clock for maliciously injected faults. It employs a pair of optimized time-to-digital converters (TDCs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3696209
Publisher: IEEE

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A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References

A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References 150 150
Author(s): Raghav Bansal, Shouri Chatterjee

Abstract:

This article presents a fully integrated output-capacitor-less (OCL) multi-feedback-loop low-dropout regulator (LDO) with an in-built single bipolar junction transistor (BJT)-based voltage and current reference (VCR) for energy-harvesting Internet of Things (IoT) devices. The proposed architecture comprises four loops, which significantly enhance the DC regulation and transient performance of the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3694415
Publisher: IEEE

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A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G

A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G 150 150
Author(s): Minzhe Tang, Dongfan Xu, Yi Zhang, Yuxuan Liu, Zheng Li, Yuncheng Zhang, Yilun Chen, Minghao Fan, Ziyuan Ren, Jian Pang, Dingxin Xu, Chenxin Liu, Daxu Zhang, Duo Li, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 21
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695546
Publisher: IEEE

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TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles

TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles 150 150
Author(s): Jacob Mack, Qirui Zhang, He Wang, Yi Shen, Jeongtaek Chang, Heejin Yang, Anjali Agrawal, Zichen Fan, Braden Desman, Zane Lewis, Thomas Farrell, David Blaauw, Will Farrell, Jim Owens, Benton H. Calhoun, Dennis Sylvester

Abstract:

Advanced smart textiles (ASTs) are textile-integrated electronic systems that enable many applications, including healthcare, robotics, and IoT. ASTs contain a variety of electronic components to enable whole system functionality (batteries, sensors, SoCs, etc.), which all require orchestration from a central command-and-control (CAC) module. The primary functions of the CAC module …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695482
Publisher: IEEE

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A Cryogenic Superconducting Quantum Computing Unit Interface Chipset With Phase-Detection-Based Readout and Phase-Shifter-Based Controller

A Cryogenic Superconducting Quantum Computing Unit Interface Chipset With Phase-Detection-Based Readout and Phase-Shifter-Based Controller 150 150
Author(s): Yanshu Guo, Yaoyu Li, Wenqiang Huang, Tian Tian, Nan Wu, Siqi Zhang, Qichun Liu, Tiefu Li, Zhihua Wang, Ning Deng, Yuanjin Zheng, Hanjun Jiang

Abstract:

This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695612
Publisher: IEEE

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PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI

PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI 150 150
Author(s): Luqi Zheng, Amir Massah Bavani, Mufeng Chen, Shuting Du, Te-Yu Hsin, Win-San Khwa, Ping-Sheng Wu, Ashwin Sanjay Lele, Bo Zhang, Brian Crafton, Harry Chuang, Yu-Der Chih, Meng-Fan Chang, Haitong Li

Abstract:

We present PROTEUS, an 18 mm2 programmable general-purpose digital compute-in-memory (GP-DCIM) accelerator integrating 4 Mb resistive random access memory (RRAM) and 2.6 Mb tensor static random access memory (SRAM) with a 32-bit hierarchical DCIM instruction set architecture (ISA). PROTEUS features fine-grained 1-D matrix tiling and a reconfigurable DCIM datapath/pipeline for near-100% memory …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3694285
Publisher: IEEE

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MIDAS: An Energy-Efficient Microscaling Quantization-Based Digital CIM Accelerator With Spatio-Temporal Cyclic Alignment for Generative AI

MIDAS: An Energy-Efficient Microscaling Quantization-Based Digital CIM Accelerator With Spatio-Temporal Cyclic Alignment for Generative AI 150 150
Author(s): Jiwon Choi, Seongyon Hong, Wooyoung Jo, Wonhoon Park, Sunjoo Whang, Seryeong Kim, Sangjin Kim, Hoi-Jun Yoo

Abstract:

Digital compute-in-memory (DCIM) and the microscaling (MX) data format have emerged as promising hardware and algorithmic solutions, respectively, for energy-efficient generative AI (GenAI) processing. However, their combination introduces challenges, including redundant computation from mantissa alignment, excessive exponent handling overhead, and accuracy loss from static approximation schemes that fail to accommodate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692361
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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