IEEE Journal of Solid-State Circuits – Early Access

  • No Comments

An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO

An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO 150 150
Author(s): Feng Bu, Depeng Sun, Dingtao Zeng, Yuan Gao, Bowen Wang, Zhicheng Dong, Xiaoteng Zhao, Hao Xu, Na Yan, Ruixue Ding, Shubin Liu, Zhangming Zhu

Abstract:

This article presents a 13-GHz quadrature charge-pump phase-locked loop (CPPLL) that simultaneously achieves ultra-low jitter and low-spur performance. First, a low-noise resistive-discharge time-amplifying phase-frequency detector (RD-TAPFD) is proposed, achieving extremely low inherent noise and significantly suppressing noise from the following stages. Second, a sampling-based dual-path loop filter effectively suppresses reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3690771
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 34 Gb/s 5 m DSP-Free PMF Active Cable in 22 nm FDSOI CMOS

A 34 Gb/s 5 m DSP-Free PMF Active Cable in 22 nm FDSOI CMOS 150 150
Author(s): Dragan Simic, Gabriel Guimarães, Valdrin Qunaj, Joren Vaes, Pieter-Antonio Fernandez, Patrick Reynaert

Abstract:

This article presents a fully integrated transmit–receive wireline communication system based on a polymer microwave fiber (PMF) as a communication medium. Operating in the D-band (110–170GHz), this system is based on coherent NRZ modulation and a non-coherent detection, including a phase-locked loop (PLL) for stable carrier generation and tunable …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687479
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Low-Jitter, Energy-Efficient 6/12-GHz PhaseInterpolator With 0.18mW/GHz in 65-nm CMOS

A Low-Jitter, Energy-Efficient 6/12-GHz PhaseInterpolator With 0.18mW/GHz in 65-nm CMOS 150 150
Author(s): Soumen Mohapatra, Emad Afshar, Zhiyuan Zhou, Deukhyoun Heo

Abstract:

This article presents a novel low-power, low-noise phase interpolator (PI) with high resolution designed for diverse applications such as local clock generation in clock data recovery (CDR) to sample time-interleaved analog-to-digital-converter (TI-ADC) and baseband delay beamforming. The proposed PI, implemented in 65-nm CMOS, utilizes a ramp signal with constant slope …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686686
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges

A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges 150 150
Author(s): Shin Han, Gicheol Shin, Jongmin Lee, Yoonmyung Lee

Abstract:

A complementary positive feedback-assisted current mirror-based level shifter (CPFLS) is proposed to reliably convert subthreshold signals to higher voltages. By adopting a positive feedback structure, the CPFLS mitigates the delay degradation and short-circuit current issues inherent in a prior art, WCMLS, due to its negative feedback design. Additionally, the CPFLS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687258
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC

A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC 150 150
Author(s): Kaiwen Zhou, Jianhong Zhou, Yijie Li, Yuying Li, Tian Dong, Zhiliang Hong, Jiawei Xu

Abstract:

A high-precision, direct-digitization sensor readout (DD-RO) based on a continuous-time delta-sigma modulator (CT- $\Delta \Sigma $ M) is presented. The proposed DD-RO incorporates several key innovations to enhance performance. First, a pseudo-differential current-balancing integrator (PD-CBI) significantly extends the linear input range, whereas its intrinsically limited common-mode input range and CMRR are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686843
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models 150 150
Author(s): Ruiqi Guo, Lei Wang, Xiaofeng Chen, Keyi Jiang, Zhiheng Yue, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Abstract:

Diffusion models have recently revolutionized the field of image synthesis due to their ability to generate photorealistic images. However, one of the main drawbacks of diffusion models is that the image generation process is expensive. Large image-to-image networks have to be applied multiple times in order to iteratively optimize the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684745
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 3.47 NEF 175.2-dB FoMs Direct Digitization Front-End Featuring Delta Amplification Noise-Shaping SAR ADC for Biosignal Acquisition

A 3.47 NEF 175.2-dB FoMs Direct Digitization Front-End Featuring Delta Amplification Noise-Shaping SAR ADC for Biosignal Acquisition 150 150
Author(s): Kyeongwon Jeong, Can Livanelioglu, Jiawei Liao, Inhee Lee, Taekwang Jang

Abstract:

This article presents a direct-digitization interface for ExG bio-signals’ readout that simultaneously achieves a high dynamic range (DR) and a low noise-efficiency factor (NEF). The proposed delta amplification (DA) and feedback cancellation technique reduce both the input and output ranges of the first amplifier, thus allowing the use of a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3685168
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise 150 150
Author(s): Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu

Abstract:

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3683111
Publisher: IEEE

View on IEEE Xplore

Search this website