IEEE Journal of Solid-State Circuits – Early Access

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging

A 16-MHz CMOS RC Frequency Reference Achieving Accuracies of ±125 ppm From −40 °C to 85 °C and −560/+580 ppm After Accelerated Aging 150 150

Abstract:

This article presents a low-power, high-accuracy CMOS RC frequency reference featuring a capacitively modulated RC time constant (CMT) generation and a die-to-die error removal (DDER) technique for precise frequency generation with a low-calibration cost. Unlike resistive trimming, the temperature dependence of the on-chip resistor is compensated by a $\Delta \Sigma $ …

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An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique

An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique 150 150

Abstract:

This article presents a discrete-time, third-order, single-loop, 17-level delta-sigma modulator (DSM) for high-dynamic-range sensor measurement applications, which employs a loop filter auto-shift (LFAS) technique. It uses an on-chip 1.5-bit Schmitt monitor to determine whether the input amplitude is large or small. The DSM automatically shifts to loop filter A for …

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A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor

A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded ΣΔ Impedance Sensor 150 150

Abstract:

Understanding complex physiological processes requires the ability to monitor multiple biological modalities concurrently, as electrical, ionic, and biochemical processes are tightly coupled and cannot be holistically described by single-mode sensors. This article presents a 40 nm CMOS multimodal cellular physiology monitoring platform that integrates 40 960 reconfigurable pixels at $10.8~\mu $ m pixel pitch. …

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A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input

A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input 150 150

Abstract:

This article presents a 32-GS/s 16-channel hierarchical time-interleaved (TI) hybrid analog-to-digital converter (ADC). The prototype utilizes the intrinsic high-speed quantization of time-domain (TD) ADC to reduce the interleaving factor. By incorporating hierarchical sampling and a cascode sampler, the compact TI-ADC achieves 44.3-dB spurious-free dynamic range (SFDR) at 20.9-GHz input. …

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A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems

A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems 150 150

Abstract:

This article proposes an envelope-tracking (ET) supply modulator (SM) that is scalable for sixth-generation (6G) communication systems. The design leverages a cost-efficient CMOS process for the power converters and a high-performance GaN process for the high-frequency power amplifier (PA) and the depletion-mode-only GaN-based amplifier. The proposed ET supply modulator (ETSM) …

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A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power

A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power 150 150

Abstract:

Targeting the wireless power transfer (WPT) to implantable medical devices (IMDs), this work presents a 6.78 MHz single-stage dual-output (SSDO) regulating rectifier. It can support the simultaneous charging of both outputs ( $V_{\text {OUT1}}$ and $V_{\text {OUT2}}$ , $V_{\text {OUT1}} \gt V_{\text {OUT2}}$ ) in a half cycle, rather than …

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Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node

Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node 150 150

Abstract:

As technology scaling increases interconnect resistance, writeability degradation in static random access memory (SRAM) becomes critical. This article presents a self-enabled write assist cell (SEWAC) that mitigates writeability degradation caused by increased bitline resistance (R ${}_{\mathrm {BL}}$ ) without requiring timing control. The SEWAC has a cell-compatible layout with the standard 6…

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

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A 0.4-V 988-nW Tiny Footprint Time-Domain Audio Feature Extraction ASIC for Keyword Spotting Using Injection-Locked Oscillators

A 0.4-V 988-nW Tiny Footprint Time-Domain Audio Feature Extraction ASIC for Keyword Spotting Using Injection-Locked Oscillators 150 150

Abstract:

This work presents an injection-locked oscillator (ILO)-based feature extraction (FEx) system. It combines voltage- and time-domain signal processing to implement a power-efficient programmable gain amplifier (PGA) and a small-footprint, high-selectivity ILO-based voltage-to-time converter bandpass filter (VTC-BPF) bank and rectifier. The VTC-BPF enables direct analog-to-time conversion, eliminating the need for …

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