IEEE Journal of Solid-State Circuits – Early Access

A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency

A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency 150 150

Abstract:

This article presents a compact 24–30-GHz phased array transceiver (TRX) front end (FE) with high transmitter (TX) power efficiency and low receiver (RX) noise figure (NF) in a 130-nm bipolar CMOS (BiCMOS) technology supporting different 5th generation mobile network (5G) frequency range 2 (FR2) bands (n257, n258, and n261). We introduce …

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A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis

A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis 150 150

Abstract:

BSTcontrol As neural network (NN) training cost red has been growing exponentially over the past decade, developing high-speed and energy-efficient training methods has become an urgent task. Fine-grained mixed-precision low-bit training is the most promising way for high-efficiency training, but it needs dedicated processor designs to overcome the overhead in …

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A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET

A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET 150 150

Abstract:

High-speed radiation-hardened frequency synthesizers are a key block in spaceborne communications systems. This article presents a 15–22-GHz radiation-hardened phase-locked loop (PLL) designed in a 22-nm FinFET process with hardening techniques for single-event upset (SEU) and total ionizing dose (TID) implemented in all key PLL blocks. Electrical performance tradeoffs arising from …

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A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications

A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications 150 150

Abstract:

This article proposes a hybrid boost converter that eliminates the right-half-plane (RHP) zero. The proposed converter can be designed with a broad bandwidth up to a tenth of the switching frequency, such that the converter can attain fast transient response as a buck converter. Besides, it features a left-half-plane zero …

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A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces 150 150

Abstract:

The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to …

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INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations

INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations 150 150

Abstract:

This article presents a 32-bit floating-point (FP32) programmable accelerator for solving a wide range of partial differential equations (PDEs) based on numerical integration methods. Compared to prior works that have fixed-point systems and are only applicable to specific types of PDEs, our proposed, integration accelerator for PDEs, named INTIACC, accelerator …

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A Single-Stage Dual-Output Regulating Voltage Doubler for Wireless Power Transfer

A Single-Stage Dual-Output Regulating Voltage Doubler for Wireless Power Transfer 150 150

Abstract:

A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD’s inherent voltage conversion ratio (VCR) …

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A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET 150 150

Abstract:

A digital-to-analog converter (DAC)-based polar transmitter (TX) is proposed for multicarrier signaling in wireline applications. The proposed TX achieves a 50-Gb/s total data rate with maximized spectral efficiency by using three parallel 5-GS/s DAC-based drivers and two orthogonal carriers of 5 and 10 GHz. The three DAC-based drivers operating …

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A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs 150 150

Abstract:

With the rapid advancement of artificial intelligence (AI), computing-in-memory (CIM) structure is proposed to improve energy efficiency (EF). However, previous CIMs often rely on INT8 data types, which pose challenges when addressing more complex networks, larger datasets, and increasingly intricate tasks. This work presents a double-bit 6T static random-access memory (…

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