IEEE Journal of Solid-State Circuits – Early Access

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A Stochastic Analog Boolean Satisfiability Solver

A Stochastic Analog Boolean Satisfiability Solver 150 150
Author(s): Shiyu Su, Qiaochu Zhang, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen

Abstract:

This article presents a stochastic analog Boolean satisfiability (SAT) solver, featuring a fast open-loop architecture with continuous-time (CT) self-loopback pull-up switches, a discrete-time (DT) scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype demonstrates 100% solvability and 3.5- $\mu $ s solution time with 8.6-nJ energy consumption for 1000 hard …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617458
Publisher: IEEE

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A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations

A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations 150 150
Author(s): Srivatsa Rangachar Srinivasa, Dileep J. Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Daniel Lake, Mikhail Moiseev, Robert Munoz, Anuradha Srinivasan, Tanay Karnik

Abstract:

The increasing adoption of chiplet-based architectures highlights the compelling paradigm of disaggregating monolithic systems into interconnected chiplets, offering numerous advantages for heterogeneous integration. This disaggregation is essential as chips approach the reticle limit, improving yield and design flexibility by combining diverse functionalities. Next-generation 2.5-D systems require enhanced interoperability across heterogeneous …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613339
Publisher: IEEE

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A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces

A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces 150 150
Author(s): Kahyun Kim, Daehoon Na, Jeongeun Song, Hajung Park, Jin-Seok Heo, Hyunjun Park, Jihee Kim, Hanseok Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi

Abstract:

This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618903
Publisher: IEEE

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A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks

A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks 150 150
Author(s): De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

Abstract:

Nonvolatile compute-in-memory (nvCIM) macros integrate memory and computation to enable high-density multiply-and-accumulate (MAC) acceleration for inference tasks on low-power edge artificial intelligence (AI) devices. Bayesian neural networks (BNNs)—which represent weights with mean ( $\mu $ ) and variance-derived deviation ( $\Delta $ )—have emerged as a promising inference model to enhance robustness against noisy …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617770
Publisher: IEEE

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A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification 150 150
Author(s): Jeroen Ponte, Roel Plompen, Emiel Zijlma, Eric A. M. Klumperink, Harijot Singh Bindra, Bram Nauta

Abstract:

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611114
Publisher: IEEE

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A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device

A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device 150 150
Author(s): Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Abstract:

The microscaling (MX) format is an emerging data representation that quantizes high-bitwidth floating-point (FP) values into low-bitwidth FP-like values with a shared-scale (SS) exponent. When implemented with computing-in-memory (CIM), MX allows an attractive tradeoff between accuracy and hardware efficiency for specific neural network (NN) workloads. This work presents the first …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617944
Publisher: IEEE

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A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications

A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications 150 150
Author(s): Woojin Hong, Hyebong Ko, Jinwoo So, Woonhyung Heo, Yonghwan Cho, Jeongdu Yoo, Ho-Sung Son, Youngwoo Chung, Dong-Joon Kim, Byeonghyeon Jin, Minkyu Kwon, Kyungmin Park, Daeyong Han, Sungkye Cho, Daewoong Cho, Jung Wook Heo, Sungwoo Lee, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu

Abstract:

Foldable mobile applications recently have been leading the battery charger to have a slim height with a small form-factor and high efficiency at higher input voltages to increase the power density. Another trend for mobile applications is the power sharing, which enables to supply two mobile devices simultaneously. To meet …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618150
Publisher: IEEE

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A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants

A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants 150 150
Author(s): Tianqi Lu, Sijun Du

Abstract:

This article presents a single-link, dual-output wireless power transfer (WPT) system operating at 40.68 MHz for miniature, high-power biomedical implants. The elevated carrier frequency enables a millimeter-scale receiver (RX) coil while maintaining link efficiency and output power comparable to low-frequency WPT designs. End-to-end (E2E) efficiency is optimized through global power …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617375
Publisher: IEEE

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A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET

A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET 150 150
Author(s): Jaewon Lee, Pier-Andrea Francese, Matthias Bräendli, Thomas Morf, Marcel Kossel, Seoyoung Jang, Yujin Choi, Donggeon Kim, Taekwang Jang, Gain Kim

Abstract:

This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( $8 \times 8$ ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618188
Publisher: IEEE

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