Voltage measurement

A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology

A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology 150 150

Abstract:

All cryo-CMOS quantum-classical control interfaces require an analog-to-digital converter (ADC) bridging the analog qubits and the digital control logic. Dynamic comparators play a crucial role in the precision, speed, and power consumption of these ADCs. Yet, their performance is severely impacted by the cryogenic environment. Therefore, this letter benchmarks, for …

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Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions

Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions 150 150

Abstract:

This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias …

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A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation

A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation 150 150

Abstract:

This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the …

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FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability

FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability 150 150

Abstract:

In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory …

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A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors

A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors 150 150

Abstract:

In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological …

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A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface 150 150

Abstract:

This work proposes a temperature and process-compensated low-power Cryo-CMOS voltage reference without trimming for quantum integrated interface, which is capable of operating continuously from room temperature (RT) down to cryogenic temperatures. By compensating for the main accuracy limiting factors including the process dependence of the transistor threshold voltage, device mismatch …

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