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A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range

A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range 150 150
Author(s): Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim

Abstract:

This article presents a three-level dual-path (TLDP) buck converter tailored for mobile application processors (APs) with a 1.8-V input and 0.4–1.5-V output range. Conventional buck (CB) and multi-level buck (MLB) converters suffer from prohibitive DC resistance ( $R_{\mathrm {DCR}}$ ) losses in compact inductors as load current increases. Although various multi-path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710310
Publisher: IEEE

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A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery 150 150
Author(s): Xuchu Mu, Yang Jiang, Xin Ming, Bo Zhang, Rui P. Martins, Pui-In Mak

Abstract:

This article presents a reconfigurable switched-capacitor (SC) DC–DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702012
Publisher: IEEE

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A Quadrature-Rotation Phased-Array Transmitter With High-Resolution Phase Tuning and Complex Domain Power Back-Off Efficiency Enhancement

A Quadrature-Rotation Phased-Array Transmitter With High-Resolution Phase Tuning and Complex Domain Power Back-Off Efficiency Enhancement 150 150
Author(s): Jie Zhou, Bingzheng Yang, Hongxin Tang, Xun Luo

Abstract:

In this article, a four-element digital-modulated phased-array transmitter based on quadrature switched/floated-capacitor power amplifiers (SFCPAs) and reconfigurable switched-capacitor tuning lines (RSCTLs) is proposed. Phase shifting in each element is achieved by hybrid coarse and fine phase-tuning approaches. The SFCPAs with the quadrature-rotation technique are presented for coarse phase tuning. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702007
Publisher: IEEE

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A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G

A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G 150 150
Author(s): Minzhe Tang, Dongfan Xu, Yi Zhang, Yuxuan Liu, Zheng Li, Yuncheng Zhang, Yilun Chen, Minghao Fan, Ziyuan Ren, Jian Pang, Dingxin Xu, Chenxin Liu, Daxu Zhang, Duo Li, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 21
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695546
Publisher: IEEE

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A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier

A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier 150 150
Author(s): Yihang Cheng, Yihan Zhang, Huaqiang Wu, Sining Pan

Abstract:

This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by $4\times $ compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier …

Published in: IEEE Solid-State Circuits Letters
Page(s): 93 – 96
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3668876
Publisher: IEEE

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A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks

A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks 150 150
Author(s): Yi Xiang Huang, Y. S. Lin, P. S. Huang, E. Ray Hsieh

Abstract:

This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive …

Published in: IEEE Solid-State Circuits Letters
Page(s): 117 – 120
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3675063
Publisher: IEEE

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A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS 150 150
Author(s): Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yong Chen

Abstract:

This article reports a 40-GS/s 8-bit time-interleaved (TI) time-domain (TD) gated-ring-oscillator analog-to-digital converter (GRO-ADC). An interleaving number of 32 is achieved with a single-channel 8-bit GRO-ADC operating at 1.25 GS/s, leading to a low front-end design complexity compared to recently published arts. The sampling front end employs a linearity-enhanced boosted …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1907 – 1920
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671459
Publisher: IEEE

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A 7-Level 18-Wire-State Trio-Signaling Transmitter for MIPI C-PHY 3.0 Interfaces

A 7-Level 18-Wire-State Trio-Signaling Transmitter for MIPI C-PHY 3.0 Interfaces 150 150
Author(s): Junyeong Lee, Myeongjin Oh, Kiwoon Kim, Jung-Hoon Chun

Abstract:

This letter presents a MIPI C-PHY v3.0 TX, which adopts trio-signaling using three wires per lane. Each line supports seven-level signaling, enabling 18 wire states to map 32-bit data into nine symbols, achieving 3.56 bits/symbol efficiency. Balanced coding maintains constant driver current, enhancing SSO noise immunity, and embedded clocking is achieved …

Published in: IEEE Solid-State Circuits Letters
Page(s): 101 – 104
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3672642
Publisher: IEEE

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A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping 150 150
Author(s): Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu

Abstract:

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {\,}-{\,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668599
Publisher: IEEE

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