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Integrated Spatiotemporal Multiscale-Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices

Integrated Spatiotemporal Multiscale-Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices 150 150
Author(s): Ziyan Liao, Zhiheng Huang, Min Xiao, Yuezhong Meng, Hui Yan, Yang Liu

Abstract:

Resistive random access memory (RRAM) is a leading candidate for next-generation nonvolatile memory and neuromorphic computing. However, its performance is limited by inherent switching variability and uncertainties in spatiotemporal multiscale materials and processes. This study integrates multiphysics and multiscale modeling with uncertainty quantification (UQ) to systematically address these limitations and …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3633067
Publisher: IEEE

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A SPICE-Compatible Compact Model of Ferroelectric Diode

A SPICE-Compatible Compact Model of Ferroelectric Diode 150 150
Author(s): Musaib Rafiq, Mohammad Sajid Nazir, Ateeb Naseer, Yogesh Singh Chauhan, Shubham Sahay

Abstract:

In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing paradigms. We propose modified Schottky barrier and hopping models for capturing the on- and off-mode operations of the FE diode, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 166 – 170
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624212
Publisher: IEEE

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3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 150 150
Author(s): Xiaosen Liu, Xichen Sun, Renwei Chen, Haozhe Zhang, Zhoutong Liu, Yan Wang

Abstract:

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 341 – 344
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624096
Publisher: IEEE

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A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth

A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth 150 150
Author(s): Basem Abdelaziz Abdelmagid, Yuqi Liu, Hua Wang

Abstract:

This work presents a compact 110–140 GHz bidirectional D-band passive phase shifter based on combining a 5-stage capacitively-loaded reflective-type PS (RTPS) with a wideband 0°/180° stage. The design achieves a 360° phase range with a resolution of 11.25°. By applying: 1) a wideband RTPS design methodology on the stage level; 2) frequency/switching-staggering techniques among the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 329 – 332
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3622233
Publisher: IEEE

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A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants

A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants 150 150
Author(s): Tianqi Lu, Sijun Du

Abstract:

This article presents a single-link, dual-output wireless power transfer (WPT) system operating at 40.68 MHz for miniature, high-power biomedical implants. The elevated carrier frequency enables a millimeter-scale receiver (RX) coil while maintaining link efficiency and output power comparable to low-frequency WPT designs. End-to-end (E2E) efficiency is optimized through global power …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617375
Publisher: IEEE

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A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

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Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 150 150
Author(s): Piyush Kumar, Da Eun Shim, Azad Naeemi

Abstract:

This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 139 – 147
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621279
Publisher: IEEE

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Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs 150 150
Author(s): Sadik Yasir Tauki, Rudra Biswas, Rakesh Acharya, Jiahui Duan, Rajiv Joshi, Kai Ni, Vijaykrishnan Narayanan

Abstract:

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 148 – 156
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619908
Publisher: IEEE

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Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model

Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model 150 150
Author(s): Mohammad Adnaan, Saeideh Alinezhad Chamazcoti, Emil Karimov, Marie Garcia Bardon, Francky Catthoor, Jan van Houdt, Azad Naeemi

Abstract:

We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM). We start with the ferroelectric capacitor device model and perform array-level memory circuit simulation. Then, we …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 99 – 106
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3618883
Publisher: IEEE

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