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A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS

A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS 150 150
Author(s): Sander Crols, Filip Tavernier, Carolina Mora Lopez, Marian Verhelst, Nick Van Helleputte

Abstract:

Solid-state nanopore single-molecule sensing aims to replace the commercially available biological nanopores. Array sizes have remained limited due to the area and power consumption of the transimpedance amplifiers (TIAs), thus preventing throughput and cost scaling. This article presents a 256-channel readout array for solid-state nanopore single-molecule sensing in 65 nm CMOS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721767
Publisher: IEEE

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Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing

Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing 150 150
Author(s): Sherif Ghozzy, Muhamed Allam, Emir Ali Karahan, Zheng Liu, Kaushik Sengupta

Abstract:

A critical challenge in scaling up high-frequency wireless communication in the millimeter-Wave (mmWave) spectrum has been poor energy efficiency of the constituent transceivers, particularly on the highly energy constrained user equipment (UE). Receiving spectrally-efficient wireless signals (e.g., 64-quadrature amplitude modulation (QAM) etc.) require coherent transceivers with programmable frequency synthesizers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720585
Publisher: IEEE

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A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation

A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation 150 150
Author(s): Yongqi Hu, Jue Huang, Chenkang Ning, Yumeng Yuan, Hao Xu, Na Yan, Xufeng Kou

Abstract:

This article presents a calibration-free fractional-N cascaded phase-locked loop (PLL) employing a sampling phase detector (SPD)-bypass-based phase-domain oversampling noise-and-spur cancellation (P-OSNSC) technique. By incorporating an oversampling cancellation path that eliminates the gain errors and noise cancellation bandwidth limitation introduced by the SPD, the proposed architecture suppresses noise from the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3725003
Publisher: IEEE

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A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

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A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 214 – 217
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

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A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM

A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM 150 150
Author(s): Nandor G. Toth, Kofi A. A. Makinwa

Abstract:

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front-end generates both PTAT and CTAT currents, whose ratio is then digitized by a continuous-time (CT) $\Delta \Sigma $ modulator, which realizes a noise-optimized current-balancing scheme that maximizes the sensor’s resolution. To correct …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721315
Publisher: IEEE

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A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration 150 150
Author(s): Tohru Kaneko, Hideaki Ishida, Yuzuru Yamaki, Satoshi Takehara, Un-Ku Moon

Abstract:

This article summarizes a calibration-free, frequency-scalable $Delta Sigma $ analog-to-digital converter (ADC) which employs dynamic open-loop integrators for low-power sensing systems. The integrators use a capacitive degeneration scheme to obtain an integration factor determined by a capacitor ratio. To enhance process-voltage-temperature (PVT) robustness, bottom-plate level shift (BPLS) and a timer are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719645
Publisher: IEEE

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A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter 150 150
Author(s): Chaoyang Xing, Yilu Cui, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This article presents a continuous-time (CT) analog-to-digital converter (ADC) featuring an incremental zoom with extended quantization architecture. The proposed MASH topology comprises an 8-bit oversampled successive-approximation register (SAR) ADC as the first stage, a 1-bit incremental CT delta-sigma modulator (CT-DSM) as the second stage, and a 12-bit Nyquist SAR ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717666
Publisher: IEEE

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A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression

A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression 150 150
Author(s): Chenyang Li, Tzu-Han Wang, Dongsuk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh S. Sathe, Shaolan Li

Abstract:

This article presents a two-step incremental analog-to-digital converter (ADC) that achieves high resolution and energy efficiency while substantially easing the input driving constraints and interstage gain variation. By employing a level-shifted sub-ranging architecture with an input-tracking (IT) feature, the design obviates direct input sampling, thereby significantly relaxing the demands on …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 884 – 897
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3635146
Publisher: IEEE

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