Noise

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator 150 150

Abstract:

This work presents a bandwidth augmented sub-sampling phase-locked loop (BASS-PLL) architecture that features simultaneous out-of-band noise suppression by direct and multipath sampling of the ring oscillator’s (ROs) output and in-band noise suppression via an intrinsic sub-sampling mechanism, ultimately combining the benefits of over-sampling PLLs (OS-PLLs) and sub-sampling PLLs (SS-PLLs) …

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Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques

Design and Analysis of Windmill-Shaping-Geometry Eight-Phase Oscillator Incorporating Magnetic and Dual-Injection Coupling Techniques 150 150

Abstract:

This article reports a compact millimeter-wave (mm-wave) quad-core eight-phase oscillator featuring magnetic coupling and dual-injection coupling. Specifically, the quad-core oscillator is integrated in an LC-ring configuration via a windmill-shaping transformer for phase noise (PN) and chip area reduction. The eight-phase oscillator could eliminate the oscillation mode ambiguity and save the …

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

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Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

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A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System

A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System 150 150

Abstract:

This article presents a pulse-width locked-loop (PWLL) time-domain readout integrated circuit (IC) for wearable strain-sensing systems based on a laser-induced graphene (LIG) strain sensor. A time-domain Wheatstone bridge (WhB) architecture is proposed, incorporating a duty-cycled resistor (DCR) and a voltage-controlled oscillator (VCO)-based integrator to realize a digitally intensive, energy-efficient, …

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A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 150 150

Abstract:

This article presents a 32-channel time-multiplexed highly digital neural recording front-end (RFE) that exhibits sub- $8.8~\mu $ s recovery latency from large stimulation artifacts while delivering high-resolution data at the Nyquist rate. The RFE is time-shared across 32 channels for low-frequency electrocorticography (ECoG) recording and across four channels for high-frequency action potentials (…

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A Self-Injection LC Oscillator for Flicker Noise Reduction

A Self-Injection LC Oscillator for Flicker Noise Reduction 150 150

Abstract:

Self-injection has been used in lasers and photonic integrated circuits to reduce the laser’s phase noise (PN). We show that self-injection can be leveraged in GHz LC oscillators as well. Our oscillator employs a current-domain self-injection technique by leveraging second-harmonic extraction, capacitive phase shifting, and self-mixing through the oscillator’…

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Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback

Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback 150 150

Abstract:

This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure p-n junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback …

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An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique

An Incremental Noise-Shaping Pipeline ADC With Single-Amplification-Based kT/C Noise Cancellation Technique 150 150

Abstract:

This article presents an incremental noise-shaping (NS) pipeline analog-to-digital converter (ADC) featuring a single-amplification-based kT/C noise cancellation technique. By pre-amplifying the frontend sampling kT/C noise onto the capacitive digital-to-analog converter (CDAC) of the backend NS successive approximation register (SAR) quantizer, the proposed architecture eliminates the repeated amplifications typically …

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