Noise

  • No Comments

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications

A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 150 150
Author(s): Yunfan Gao, Minghan Liu, Mengting Yan, Cristian Cassella, Miriam Leeser, Marvin Onabajo

Abstract:

This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct downconversion mixing, which avoids a dedicated LO generator, coupler, or …

Published in: IEEE Solid-State Circuits Letters
Page(s): 258 – 261
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3725828
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Current-Mode Non-Destructive Circuit Readout Scheme for High-Density 3D Ferroelectric Memory

A Current-Mode Non-Destructive Circuit Readout Scheme for High-Density 3D Ferroelectric Memory 150 150
Author(s): CHaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick Van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan Van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3D-stacked ferroelectric memory (FeRAMs) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS

A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS 150 150
Author(s): Sander Crols, Filip Tavernier, Carolina Mora Lopez, Marian Verhelst, Nick Van Helleputte

Abstract:

Solid-state nanopore single-molecule sensing aims to replace the commercially available biological nanopores. Array sizes have remained limited due to the area and power consumption of the transimpedance amplifiers (TIAs), thus preventing throughput and cost scaling. This article presents a 256-channel readout array for solid-state nanopore single-molecule sensing in 65 nm CMOS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721767
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing

Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing 150 150
Author(s): Sherif Ghozzy, Muhamed Allam, Emir Ali Karahan, Zheng Liu, Kaushik Sengupta

Abstract:

A critical challenge in scaling up high-frequency wireless communication in the millimeter-Wave (mmWave) spectrum has been poor energy efficiency of the constituent transceivers, particularly on the highly energy constrained user equipment (UE). Receiving spectrally-efficient wireless signals (e.g., 64-quadrature amplitude modulation (QAM) etc.) require coherent transceivers with programmable frequency synthesizers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720585
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation

A −251.4-dB FoM Calibration-Free Fractional-N Cascaded PLL With Wideband Oversampling Noise-and-Spur Cancellation 150 150
Author(s): Yongqi Hu, Jue Huang, Chenkang Ning, Yumeng Yuan, Hao Xu, Na Yan, Xufeng Kou

Abstract:

This article presents a calibration-free fractional-N cascaded phase-locked loop (PLL) employing a sampling phase detector (SPD)-bypass-based phase-domain oversampling noise-and-spur cancellation (P-OSNSC) technique. By incorporating an oversampling cancellation path that eliminates the gain errors and noise cancellation bandwidth limitation introduced by the SPD, the proposed architecture suppresses noise from the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3725003
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 214 – 217
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM

A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM 150 150
Author(s): Nandor G. Toth, Kofi A. A. Makinwa

Abstract:

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front-end generates both PTAT and CTAT currents, whose ratio is then digitized by a continuous-time (CT) $\Delta \Sigma $ modulator, which realizes a noise-optimized current-balancing scheme that maximizes the sensor’s resolution. To correct …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721315
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration 150 150
Author(s): Tohru Kaneko, Hideaki Ishida, Yuzuru Yamaki, Satoshi Takehara, Un-Ku Moon

Abstract:

This article summarizes a calibration-free, frequency-scalable $Delta Sigma $ analog-to-digital converter (ADC) which employs dynamic open-loop integrators for low-power sensing systems. The integrators use a capacitive degeneration scheme to obtain an integration factor determined by a capacitor ratio. To enhance process-voltage-temperature (PVT) robustness, bottom-plate level shift (BPLS) and a timer are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719645
Publisher: IEEE

View on IEEE Xplore

Search this website