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A High-Voltage Symbol-Power-Tracking Supply Modulator for 5G GaN Power Amplifiers

A High-Voltage Symbol-Power-Tracking Supply Modulator for 5G GaN Power Amplifiers 150 150
Author(s): Changjin Chen, Minghao Shang, Yichao Ji, Qingqing Min, Chunyue Bo, Lin Cheng

Abstract:

This article presents a high-voltage symbol-power-tracking supply modulator (SPT-SM) that delivers a wide output range for 5G gallium nitride (GaN) power amplifiers (PAs). To enhance the output voltage transition speed, a two-step subranging dynamic voltage scaling (DVS) scheme and an inductor current slew-rate enhancement technique are proposed. By partitioning the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3731511
Publisher: IEEE

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A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications

A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications 150 150
Author(s): Mohamed Eleraky, Alessandro Novello, Giorgio Cristiano, Basem Abdelaziz Abdelmagid, Yuqi Liu, Jianping Zeng, Jinglong Xu, Boce Lin, Jonas Nann, Hangxing Liu, Marco Saif, Niccolò Villaggi, Lavinia Recchioni, Tzu-Yuan Huang, Thomas Burger, Thomas Kleier, Hua Wang

Abstract:

This article presents an eight-channel dual-polarized Ku-band transmitter (Tx) beamformer integrated circuit (BFIC) fabricated in a 22-nm GlobalFoundries FDSOI process. Each channel integrates independent phase and gain control utilizing a 7-bit active phase shifter (PS) and a 5.5-bit attenuator (ATT). To mitigate performance degradation caused by load impedance variations in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3727539
Publisher: IEEE

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A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS

A 256-Channel Solid-State Nanopore Readout Array With 193-pA TIAs and Event Detection at 1-MHz in 65-nm CMOS 150 150
Author(s): Sander Crols, Filip Tavernier, Carolina Mora Lopez, Marian Verhelst, Nick Van Helleputte

Abstract:

Solid-state nanopore single-molecule sensing aims to replace the commercially available biological nanopores. Array sizes have remained limited due to the area and power consumption of the transimpedance amplifiers (TIAs), thus preventing throughput and cost scaling. This article presents a 256-channel readout array for solid-state nanopore single-molecule sensing in 65 nm CMOS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721767
Publisher: IEEE

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Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback

Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback 150 150
Author(s): Luke D. Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn

Abstract:

Boolean satisfiability (SAT or $k$ -SAT, $k ge 3$ ) is a binary combinatorial optimization problem (COP) that is challenging for traditional classical computing to address in polynomial time. Quantum and quantum-inspired systems have been touted to tackle these and similar nondeterministic polynomial-time (NP) problems. This work describes Medusa, a quantum-inspired $k$ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726445
Publisher: IEEE

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A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential pulse-amplitude modulation (PAM-3) transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard …

Published in: IEEE Solid-State Circuits Letters
Page(s): 234 – 237
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 214 – 217
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

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A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM

A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM 150 150
Author(s): Nandor G. Toth, Kofi A. A. Makinwa

Abstract:

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front-end generates both PTAT and CTAT currents, whose ratio is then digitized by a continuous-time (CT) $\Delta \Sigma $ modulator, which realizes a noise-optimized current-balancing scheme that maximizes the sensor’s resolution. To correct …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721315
Publisher: IEEE

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