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A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation

A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation 150 150
Author(s): Ahmet Yusuf Salim, Soner Seçkiner, Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse

Abstract:

Recent years have seen growing interest in custom and nature-inspired computing methods for solving computationally challenging combinatorial optimization problems. The Boolean satisfiability (SAT), a canonical nondeterministic polynomial (NP)-complete problem, has remained a focal point due to its wide applicability in artificial intelligence, cryptography, and formal verification. This article presents …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721413
Publisher: IEEE

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A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation

A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation 150 150
Author(s): Tianxiang Qu, Nan Wang, Zuo Zhang, Longxi Xiang, Ting Yi, Zhiliang Hong, Xiaoyang Zeng, Jiawei Xu

Abstract:

This article presents a high-precision tunnel magnetoresistance (TMR)-based non-contact current sensor with enhanced immunity to sensitivity drift. A background sensitivity stabilization loop (SSL) continuously regulates the TMR bias voltage to compensate intrinsic sensitivity variations. Through this closed-loop regulation, sensitivity drift of the TMR sensor induced by temperature, mechanical stress, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719689
Publisher: IEEE

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A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter

A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter 150 150
Author(s): Jiacheng Yang, Zihao Tang, Rui P. Martins, Zheng Wang, Lin Cheng, Mo Huang

Abstract:

This article presents a line-connected Q-sampler-based (LQS) multi-phase (MP) hybrid converter for direct conversion from high-rail to point-of-load (PoL). The proposed topology uses an input-parallel switched-capacitor (SC) structure to support “ALL-ON” operation during load transients, while a “multi-source- ${V}_{\mathrm { X}}$ ” control decouples voltage conversion ratio (VCR) from phase count, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718696
Publisher: IEEE

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A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz

A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz 150 150
Author(s): Heng Ma, Huajun Zhang, Yuyan Liu, Qinwen Fan

Abstract:

This article presents a fully integrated shunt-resistor-based in-line current sensor for high-voltage (HV) pulse-width modulation (PWM)-based power systems. Floating-Gm current sensors are effective at rejecting HV PWM common-mode (CM) interference, but their linearity degrades at high CM voltages due to the substrate current-induced body effect (SCBE) in HV laterally …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3716767
Publisher: IEEE

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A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer

A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer 150 150
Author(s): Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This work presents a pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a current-buffer-based integrating sampler that combines an easy-to-drive resistive input with high linearity. To overcome the linearity and swing limitations of conventional current-integrating samplers (CISs), the frontend employs a $G_{m}$ -boosted continuous-time (CT) floating charge transferrer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714848
Publisher: IEEE

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A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

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Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning

Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning 150 150
Author(s): M. Drouhin, M. Grelier, M. Deroo, Y. Sassi, E. Monteblanco, N. Davila, G. Mihajlović, R. V. Chopdekar, T. S. Santos, J. A. Katine, D. Ravelosona

Abstract:

Artificial neural networks (ANNs) have enabled major advances in artificial intelligence, yet their growing computational and energy demands challenge conventional von Neumann architectures due to the costly separation of memory and processing. In-memory computing has emerged as a promising solution, particularly through memristive crossbar arrays capable of performing multiply-and-accumulate operations …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 129 – 134
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3702001
Publisher: IEEE

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Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150
Author(s): Sining Pan, Xiaohan Liu, Ziyi Li, Minge Jiang, Yihang Cheng, Zhong Tang, Huaqiang Wu

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711071
Publisher: IEEE

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A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 150 150
Author(s): Guo Wei, Rui Zhang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This letter presents a 12-bit, 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for a fast-response characteristic, a high-gain residue amplifier (RA) featuring a two-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The …

Published in: IEEE Solid-State Circuits Letters
Page(s): 186 – 189
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697220
Publisher: IEEE

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