Current

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

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A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs

A Low-Quiescent-Current, Low-Ripple Hybrid Converter With Efficient Energy Recycling for Low-Duty-Cycle SoCs 150 150

Abstract:

This article presents a modified hybrid Ladder converter for efficient energy recycling in low-duty-cycle systems-on-chip (SoCs) applications. Unlike the conventional schemes that recycle output-capacitor energy back to the battery, the proposed hybrid converter recycles energy into its own capacitors, eliminating battery-recharge losses and improving recycle/recharge efficiency. The design methodology …

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Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing

Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing 150 150

Abstract:

The growing demand for energy-efficient computing has intensified interest in highly scalable device technologies such as complementary field-effect transistors (CFETs). In this work, we investigate S-curve engineering for a unique ferroelectric-on-top (FE-o-T) negative-capacitance (NC) CFET through calibrated numerical simulations to assess its potential for ultra-low-power computing and supply-voltage scaling. Our …

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A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation

A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation 150 150

Abstract:

This article presents a 28-nm CMOS 1-chip LED-on-Silicon (LEDoS) backplane (BP) for 6652-pixel-per-inch (PPI) microLED ( $mu $ LED) augmented reality (AR) displays. To address power and display quality challenges in AR glasses, the proposed BP employs two low-power techniques: self-refresh and partial update, and introduces four display quality enhancement methods: MSB …

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Probabilistic Computing With Neuromorphic Elements

Probabilistic Computing With Neuromorphic Elements 150 150

Abstract:

This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

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One-Cycle-Balance Control in Buck Converters for Consecutive Load-Step Events

One-Cycle-Balance Control in Buck Converters for Consecutive Load-Step Events 150 150

Abstract:

One-cycle-balance (OCB) response represents the optimal load-transient response for buck converters, maximizing system energy efficiency and robustness. While prior art has demonstrated OCB response for single load-step events, it fails in consecutive transients, which are prevalent in modern applications. This work overcomes these limitations by introducing an OCB controller that …

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A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring

A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring 150 150

Abstract:

A fully integrated multimodal biosensing system-on-chip (SoC) for stress monitoring is presented. The proposed SoC integrates electrocardiography (ECG), electrochemical (ECH), photoplethysmography (PPG), and galvanic skin response (GSR) sensing together with an on-chip transmitter (TX), wake-up receiver (WuRX), and power-management unit (PMU) for compact, standalone operation. ECG and ECH share a …

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A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry

A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry 150 150

Abstract:

Existing single-link wireless power and data transfer (WPDT) systems for implantable biosensors support either closed-loop power regulation or sensor data uplink, but not both simultaneously, resulting in degraded efficiency and restricted sensing. This work presents a 13.56-MHz WPDT system with: 1) a synchronized phase-shifted time-multiplexed uplink scheme enabling TX power regulation …

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