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Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback

Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback 150 150
Author(s): Luke D. Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn

Abstract:

Boolean satisfiability (SAT or $k$ -SAT, $k ge 3$ ) is a binary combinatorial optimization problem (COP) that is challenging for traditional classical computing to address in polynomial time. Quantum and quantum-inspired systems have been touted to tackle these and similar nondeterministic polynomial-time (NP) problems. This work describes Medusa, a quantum-inspired $k$ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726445
Publisher: IEEE

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A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential pulse-amplitude modulation (PAM-3) transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard …

Published in: IEEE Solid-State Circuits Letters
Page(s): 234 – 237
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 214 – 217
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

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A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM

A Self-Calibrated NPN-Based Temperature Sensor With ±0.05 °C (3σ) Inaccuracy From −70 °C to 125 °C and 100fJ ${\\cdot}$ K2 Resolution FoM 150 150
Author(s): Nandor G. Toth, Kofi A. A. Makinwa

Abstract:

This article presents a CMOS temperature sensor that achieves both state-of-the-art energy efficiency and accuracy. An NPN-based front-end generates both PTAT and CTAT currents, whose ratio is then digitized by a continuous-time (CT) $\Delta \Sigma $ modulator, which realizes a noise-optimized current-balancing scheme that maximizes the sensor’s resolution. To correct …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721315
Publisher: IEEE

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A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation

A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation 150 150
Author(s): Tianxiang Qu, Nan Wang, Zuo Zhang, Longxi Xiang, Ting Yi, Zhiliang Hong, Xiaoyang Zeng, Jiawei Xu

Abstract:

This article presents a high-precision tunnel magnetoresistance (TMR)-based non-contact current sensor with enhanced immunity to sensitivity drift. A background sensitivity stabilization loop (SSL) continuously regulates the TMR bias voltage to compensate intrinsic sensitivity variations. Through this closed-loop regulation, sensitivity drift of the TMR sensor induced by temperature, mechanical stress, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719689
Publisher: IEEE

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A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation

A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation 150 150
Author(s): Ahmet Yusuf Salim, Soner Seçkiner, Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse

Abstract:

Recent years have seen growing interest in custom and nature-inspired computing methods for solving computationally challenging combinatorial optimization problems. The Boolean satisfiability (SAT), a canonical nondeterministic polynomial (NP)-complete problem, has remained a focal point due to its wide applicability in artificial intelligence, cryptography, and formal verification. This article presents …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721413
Publisher: IEEE

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A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter

A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter 150 150
Author(s): Jiacheng Yang, Zihao Tang, Rui P. Martins, Zheng Wang, Lin Cheng, Mo Huang

Abstract:

This article presents a line-connected Q-sampler-based (LQS) multi-phase (MP) hybrid converter for direct conversion from high-rail to point-of-load (PoL). The proposed topology uses an input-parallel switched-capacitor (SC) structure to support “ALL-ON” operation during load transients, while a “multi-source- ${V}_{\mathrm { X}}$ ” control decouples voltage conversion ratio (VCR) from phase count, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718696
Publisher: IEEE

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