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A 39.4mW 300MHz-BW 70.9dB-SNDR Hybrid ADC With Resistive Input and 200fs,rms-Jitter Tolerance

A 39.4mW 300MHz-BW 70.9dB-SNDR Hybrid ADC With Resistive Input and 200fs,rms-Jitter Tolerance 150 150
Author(s): Yanquan Luo, Mingtao Zhan, Yi Zhong, Nan Sun

Abstract:

This paper presents a power-efficient hybrid ADC architecture: a low-resolution CT Delta-Sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback provides a high jitter-immunity; the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656180
Publisher: IEEE

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This paper presents a low-jitter digital harmonic-mixing fractional-N phase-locked loop (PLL) using a ring oscillator (RO). To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector (PD) and delta-sigma modulator (DSM). Furthermore, to reduce mixing …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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A Self-Injection LC Oscillator for Flicker Noise Reduction

A Self-Injection LC Oscillator for Flicker Noise Reduction 150 150
Author(s): Bahram Jafari, Ali Ghafari, Sankaran Aniruddhan, Shahriar Mirabbasi, Sudip Shekhar

Abstract:

Self-injection has been used in lasers and photonic integrated circuits to reduce the laser’s phase noise (PN). We show that self-injection can be leveraged in GHz LC oscillators as well. Our oscillator employs a current-domain self-injection technique by leveraging second-harmonic extraction, capacitive phase shifting, and self-mixing through the oscillator’…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3643322
Publisher: IEEE

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A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks

A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks 150 150
Author(s): Chaorong Wang, Quan Pan, Xiaohu Fang

Abstract:

This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard $\pi $ -type equivalent circuits often suffer from bandwidth degradation due to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 21 – 24
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3646815
Publisher: IEEE

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BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator 150 150
Author(s): Tong Zhang, Yiwen Zhang, Xueke Cai, Weihao Jie, Yanling Zheng, Deyong Li, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang

Abstract:

This work presents a bandwidth augmented sub-sampling phase-locked loop (BASS-PLL) architecture that features simultaneous out-of-band noise suppression by direct and multipath sampling of the ring oscillator’s (ROs) output and in-band noise suppression via an intrinsic sub-sampling mechanism, ultimately combining the benefits of over-sampling PLLs (OS-PLLs) and sub-sampling PLLs (SS-PLLs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3640726
Publisher: IEEE

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A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and −56 dBc Spur

A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and −56 dBc Spur 150 150
Author(s): Jaewon Oh, Cheol So, Hyojun Kim, Songcheol Hong, SeongHwan Cho

Abstract:

This article presents a fast-settling 60-GHz local oscillator (LO) for stepped-carrier orthogonal frequency-division multiplexing (OFDM), employing an I/Q-calibrated single-sideband (SSB) mixer with a frequency-tuned injection-locked oscillator (ILO) filter. The SSB mixer enables instantaneous frequency hopping, while the ILO acts as a high- $Q$ bandpass filter that suppresses mixer-induced spurs. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3634591
Publisher: IEEE

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A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs

A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs 150 150
Author(s): Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Youngsun Song, Chung-Ho Yu, Hirano Makoto, Yongseok Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Philkyu Kang, Byungrok Go, Minseok Kim, Seoyoon Jeon, Jaehwan Ryu, Jungmin Seo, Hwan-Seok Ku, Youngmin Jo, Doo-Hyun Kim, Hyunjun Yoon, Wontae Kim, Inmo Kim, Sunghoon Kim, Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Youngdon Choi, Il-Han Park, Chiweon Yoon, Hyunsuk Kim, Jaehoon Jang, Seungjae Lee, Ki-Whan Song, Sung-Hoi Hur

Abstract:

The challenge of evolving to create a memory that is shrinking compared to the previous generation while satisfying the high performance and low power required for flash memory has been present in every generation, but the recent rapid change to artificial intelligence (AI) trends is very tough, as the level …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 9
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613774
Publisher: IEEE

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3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency

3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency 150 150
Author(s): Janak Sharda, Madison Manley, Jungyoun Kwak, Chinsung Park, Muhannad Bakir, Shimeng Yu

Abstract:

Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures, such as 2.5-D integration of memory with logic, have been proposed; however, the bandwidth limits the throughput of the complete system. Recent works have proposed memory on logic systems, where high bandwidth memory (HBM) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 116 – 122
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617298
Publisher: IEEE

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