Bandwidth

  • No Comments

A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity

A 15-MHz, 2.7-mm2 Notch-Free Hybrid Magnetic Current Sensor With Feedforward Ripple Cancellation and ±0.8% Local Gain Non-Uniformity 150 150
Author(s): Feng Cheng, Jianlin Xia, Encheng Zhu, Long Zhang, Zhongyuan Fang, Xiaofeng Sun, Dejin Wang, Shaoping Li, Jing Zhu, Yongjia Li, Weifeng Sun

Abstract:

This article proposes a hybrid magnetic current sensor achieving a 15-MHz bandwidth within a compact 2.7-mm2 area. To mitigate the pole–zero mismatch inherent in the two-stage integrator topology, a dual-output Gm-C integrator with subtractor-based compensation is proposed, achieving a ±0.8% local gain non-uniformity. A wideband feedforward ripple suppression scheme cancels …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3692476
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping 150 150
Author(s): Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu

Abstract:

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {\,}-{\,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668599
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency

Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency 150 150
Author(s): Sukbin Lim, Jung-Hoon Kim, Seungjae Moon, Junseo Cha, Dongjin Seo, Jongho Kim, Hunjong Lee, Jinwon Lee, Joo-Young Kim

Abstract:

The proliferation of large language models (LLMs) as cross-domain foundation models is fueled by aggressive scaling in both parameter counts and inference-time computation. The emergence of sophisticated reasoning models further accelerates this trend, demanding longer context windows and escalating the computational and memory burdens of inference. A fundamental challenge arises …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1513 – 1525
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663603
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination

A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination 150 150
Author(s): Bo Pang, Fei You, Taotao Pang, Rongxing Qin, Zehua Xiao, Yingjie Liu, Yingyu Liu, Xinyu Wang, Junfu Guo, Songbai He

Abstract:

This article presents a 2–18 GHz high-efficiency CMOS nonuniform distributed power amplifier (NDPA) with a novel reconfigurable inductive termination technique for ultra-broadband efficiency enhancement. First, the inherent drawback of the degrading efficiency with growing frequency in a conventional non-reconfigurable NDPA architecture with multi-octave bandwidth is studied. A simple and effective reconfigurable …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665920
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O

A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O 150 150
Author(s): Ganesh Balamurugan, Parmanand Mishra, Subal Sahni, Ankur Aggarwal, Simon Forey, Andrew Gimlett, Prateek Goyal, Han Hao, Santosh Hariwan, Masum Hossain, Sejun Jeon, Narayan Kaniyur, David Lazovsky, Wonho Lee, Bengt Littmann, Raj Nagulapalli, Kevin Park, John Rollinson, Matteo Staffaroni, Prakash Thakur, Saurabh Vats, Preet Virk, Dehua Xiao, Hemesh Yasotharan, Raman Yazdani, Waleed Younis, Shifeng Yu, Phil Winterbottom

Abstract:

This work presents a hybrid 3-D-integrated silicon photonic (SiPh) transceiver suitable for realizing chiplet-based optical I/O in future AI/ML ASIC packages. The optical transceiver die stack is composed of two ICs: a SiPh IC (PIC) with micrometer-scale, thermally robust electro-absorption modulators (EAMs), and a 5-nm CMOS electronic IC (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655295
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET

A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET 150 150
Author(s): Didem Turker Melek, James Vandersand, R. Navin Kumar, Pyare M. Sarkar, Prakash BS, Adrian Leuciuc, Kevin Geary, Shaojun Ma, Chirag M. Mehta, Basant Bothra, Shashi Jain, Pawan Sabharwal, Ranjan Vaish, Kirti Bhanushali, Yutong Ding, Craig Frost, John Annunziata, Krishanu Sadhu, Dimitris Kyritsis, Jeff Bostak, Ming Li, Steve Williams, Ken Chang

Abstract:

This work presents two die-to-die (D2D) wireline transceivers, one compliant with the UCIe advanced package (UCIe-AP) and the other with the UCIe standard package (UCIe-SP) standard, developed in 3 nm FinFET. The Universal Chiplet interconnect express (UCIe)-AP link has 64 RX and 64 TX data lanes in one PHY module and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651425
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay

A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay 150 150
Author(s): Giovanni Scarlato, John R. Long

Abstract:

A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with $12~\pm ~2$ -ps group delay and >10-dB return loss across 90 GHz. Bandwidth …

Published in: IEEE Solid-State Circuits Letters
Page(s): 65 – 68
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3661366
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm 150 150
Author(s): Brian Zimmer, Stephen G. Tell, C. Thomas Gray

Abstract:

This work presents a self-timed die-to-die link that serializes four data bits per pin for 2.5-D, or 3-D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of one cycle, energy efficiency of 77 fJ/b, and bandwidth density of 44…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658215
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 3-D HBI Compliant 1.536 TB/s/mm2 Bandwidth Scalable Attention Accelerator With 22.5-GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3

A 3-D HBI Compliant 1.536 TB/s/mm2 Bandwidth Scalable Attention Accelerator With 22.5-GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3 150 150
Author(s): Prerna Budhkar, Mirco Sciulli, Srivatsa Rangachar Srinivasa, Gauthaman Murali, Ragh Kuttappa, Paolo Aseron, Trang Nguyen, Vinayak Honkote, Tanay Karnik

Abstract:

This letter presents a novel hardware accelerator compatible with <3- $\mu $ m pitch 3-D Cu-Cu hybrid bonding interconnect (HBI) technology, particularly designed to efficiently execute multihead attention (MHA) of encoder transformer models. We present an accelerator that addresses performance losses due to low precision models by incorporating specialized hardware optimizations …

Published in: IEEE Solid-State Circuits Letters
Page(s): 69 – 72
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3659575
Publisher: IEEE

View on IEEE Xplore

Search this website