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A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS 150 150
Author(s): Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan

Abstract:

A 2 $times$ 56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active crosstalk extraction (A-XTCR) is proposed to improve the signal reutilization efficiency of the RX. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387355
Publisher: IEEE

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A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications
A 2.8 $\mu$ s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications 150 150
Author(s): Junyi Ruan, Junmin Jiang, Chenzhou Ding, Yunxiao Li, Yanhui Wu, Ka Nang Leung, Xun Liu

Abstract:

This article proposes a hybrid boost converter that eliminates the right-half-plane (RHP) zero. The proposed converter can be designed with a broad bandwidth up to a tenth of the switching frequency, such that the converter can attain fast transient response as a buck converter. Besides, it features a left-half-plane zero …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3376251
Publisher: IEEE

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Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications
Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications 150 150
Author(s): Jonah Van Assche, Georges Gielen

Abstract:

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3373553
Publisher: IEEE

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A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators 150 150
Author(s): Martijn Timmermans, Kyle van Oosterhout, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore

Abstract:

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1194 – 1203
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3352735
Publisher: IEEE

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