• SSCS December Technical Webinar: How Close Should Compute and Memory Be?

    Online
    Virtual Event

    Abstract: Compute-in-memory (CIM) and processing-near-memory (PNM) have emerged as promising approaches to overcome the limitations of architectures that separate processing from memory. While this bottleneck is often attributed to von Neumann’s design, such critiques overlook its historical significance: the separation of logic and memory enabled the decoupling of software from hardware, laying the foundation for general-purpose […]

  • OJ-SSCS: How to Design a Differential LC Oscillator | SSCS January Technical Webinar

    Online
    Virtual Event

    Abstract: This presentation will elaborate on some of the technical content of the paper of the same title published in the OJSSCS. The paper employs several methods that may be unfamiliar to readers. They are: How to separate PM from AM in a noise spectrum How to formulate approximate transfer functions for circuits subject to periodic […]

  • JxCDC: Weight-Input Transformations for Robust and Low Power CiM in Ultra-Low Precision DNNs | SSCS February Technical Webinar

    Virtual Event

    Abstract: Computing-in-memory (CiM), in conjunction with ultra-low precision (ULP) inputs and weights, promises a pathway towards the deployment of DNN workloads on resource-constrained edge platforms. For instance, CiM-enabled binary neural network (BNN) accelerators (with inputs and weights quantized to two states: {-1,1}) have shown potential by significantly reducing storage and energy cost while maintaining acceptable […]

  • Algorithm-Driven Physical Design Automation for 3D Integrated Circuits | SSCS March Technical Webinar

    Online
    Virtual Event

    Abstract: Three-dimensional integrated circuits (3D ICs) are shaping the future of AI hardware by stacking multiple chips vertically to achieve higher bandwidth, lower latency, and better energy efficiency. But this vertical integration also introduces new design challenges, including heat dissipation, power delivery, cross-layer timing, clock distribution, routing congestion, and multi-physics reliability, making manual design impractical. […]

  • Ideas for Extreme Energy Efficiency for Analog Circuits | SSCS April Technical Webinar

    Online
    Virtual Event

    Abstract: With emerging trends such as machine learning, the internet of everything, brain–machine interfaces, autonomous driving, 6G communications, and quantum computing, circuit designers are increasingly challenged to achieve drastic improvements in accuracy, speed, and power efficiency. Yet, as CMOS circuit designs have matured over the past five decades, we often find ourselves constrained by well-established […]

  • The Continuous-Time Pipeline ADC: Where Filtering Meets Analog-to-Digital Conversion | SSCS June Technical Webinar

    Online

    Abstract: Analog-to-digital converters that incorporate inherent anti-alias filtering and are easy to drive significantly simplify system design. The continuous-time pipelined (CTP) ADC is one such architecture — and it turns out to be a fundamental improvement over the conventional active filter followed by ADC cascade, both in power efficiency and linearity. This tutorial traces the […]