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Abstract: Today’s complex systems for high-performance computing feature chiplets using advanced packaging technologies, commercially known as EMIB, CoWoS, InFO, FOCoS, and several others from multiple sources. These 2D/2.5D structures require ultra-dense I/O PHYs to deliver a large amount of data between dice over a distance of a few millimeters without adding much power and area penalty to each die.
This talk will highlight several important use cases of chiplets for AI and data centers, and then delve deeper into the latest trends in I/O circuit designs for chiplets. It will also discuss ongoing standardization efforts and I/O circuits for 3D integrations.
Register here: https://ieee.webex.com/weblink/register/rfd50243fa84a557cf9fb9d0c7533b010
Biography: Yoshinori Nishi received the B.S. and M.S. degrees in low-temperature physics from Waseda University in Tokyo, Japan, in 1997 and 1999, respectively.
From 1999 to 2003, he was with NTT Electronics, Inc. as a member of ultra-high-speed device development group where he was Chief Designer for the 50Gb/s InP HEMT logic family, first 50Gb/s product in the market in 2001.
In 2003, he joined Kawasaki Microelectronics Inc. R&D division where he led the development of 10Gb/s Burstmode CDR for 10G-EPON application as Chief Architect, also first in the market in 2009.
He joined Nvidia Corp. in 2011 and led one of NVLINK PHY design teams for 8 years before he joined NVIDIA Research in 2020. His current research focuses on ultra-low power, high-density interconnect for chiplets.