Register here: https://ieee.webex.com/weblink/register/raf95ee78000bd7ad20cf435926c4905c
Organized by: Maurits Ortmanns
Co-sponsored by: IEEE Electron Devices Society, IEEE Reliability Society
Agenda:
Radiation Effects on semiconductors components. Soumyajit Mandal, BNL. 30 min + 5min Q&A
Radiation Hardening By Design (RHBD) in CMOS standard process. Cristiano Calligaro, RedCat Devices. 30 min + 5min Q&A
On-Chip Infrastructure for Mission-Mode Monitoring of Resilient Systems: towards Silicon Lifecycle Management. Fabian Vargas, Senior Scientist, IHP – Microelectronics, Germany. 30 min + 5min Q&A
Matrix Radiation Sensors in a standard CMOS technology. Yakov Roizin, Tower Seminconductor. 30 min + 5min Q&A
Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments Philip Neudeck, NASA. 30 min + 5min Q&A
ESA programs and standards for ASIC, FPGA and IP Cores for space. Agustin Fernandez Leon, ESA. 30 min + 5min Q&A
Abstract:
This workshop on Solid State Circuits and Devices in Radiation Environments explores the challenges and design techniques for developing reliable semiconductor components and integrated circuits for harsh radiation conditions, such as those encountered in space, nuclear, and high-energy physics environments. Participants will gain in-depth insights into the basics and latest advancements in radiation-hardened design approaches and technologies, with a focus on several key topics:
- Radiation Effects on semiconductors components, Soumyajit Mandal
Abstract: This talk will introduce the main effects of high-energy radiation on semiconductor detectors and integrated circuits. Broadly speaking, these effects can be categorized into stochastic and cumulative damage mechanisms. The former are typically caused by individual ionizing particles and are thus known as single event effects (SEEs), while the latter are functions of both the total ionizing dose (TID) received by the chip and the accumulation of displacement damage within the semiconductor lattice. The occurrence and properties of radiation-induced damage will be discussed in the context of the radiation environments experienced by electronics in three important applications, namely space missions, nuclear reactors, and particle accelerators. The impact of process scaling and prospects for the future will also be presented.
Bio: Soumyajit Mandal (Senior Member, IEEE) received the B.Tech. degree from Indian Institute of Technology (IIT) Kharagpur, India, in 2002, and the M.S. and Ph.D. degrees in electrical engineering from Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, in 2004 and 2009, respectively. He was a Research Scientist with the Schlumberger-Doll Research, Cambridge, from 2010 to 2014; an Assistant Professor with the Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, USA, from 2014 to 2019; and an Associate Professor with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA, from 2019 to 2021. He is currently a Research Staff Member with the Instrumentation Division, Brookhaven National Laboratory, Upton, NY, USA. He has more than 175 publications in peer-reviewed journals and conferences and has been awarded 26 patents. His current research interests include precision instrumentation for various radiation sensing and biomedical device applications, low-power analog and RF circuits, analog and biological computing, and magnetic resonance sensors. He was a recipient of the President of India Gold Medal, in 2002; the MIT Microsystems Technology Laboratories (MTL) Doctoral Dissertation Award, in 2009; the T. Keith Glennan Fellowship, in 2016; and the IIT Kharagpur Young Alumni Achiever Award, in 2018.
- Radiation Hardening By Design (RHBD) in CMOS standard process, Cristiano Calligaro
Abstract: In this talk an overiview on the most common techniques for radiation hardening by design (RHBD) will be discussed with a specific focus on standard CMOS process available in nodes from 250nm down to 28nm. Both TID and SEE mitigation strategies at architecture, circuit and layout level will be described showing practical examples in standard cells, SRAMs and analog devices (e.g. data converters).
Bio: Cristiano Calligaro received the laurea degree in Electronics Engineering and the Ph.D. degree in Electronics and Information Technology Engineering from the University of Pavia (Italy) in 1992 and 1997 respectively. After obtaining the Ph.D. degree he moved to MAPP Technology. In 2006 he established RedCat Devices srl as a start-up. During his career he has been involved in memory design (volatile and non volatile) both for consumer application (multilevel flash memories) and space applications (rad-hard memories) and software design for SEE/TID evaluation using open source EDA tools. His current research interest is focused on rad-hard standard cell libraries to be used for rad-hard mixed signal ASICs, stand-alone memories (SRAMs and NVMs) and testing methodologies for rad-hard components. He holds more than 20 patents mainly in the field of multilevel NVMs and is co-author of more than 60 papers and one book (Rad-hard Semiconductor Memories, River Publishers). He has been coordinator of RAMSES and ATENA projects inside the Italy-Israel Cooperation Programme, SkyFlash project in the European FP7 Programme, EuroSRAM4Space project in the Eureka Eurostars Programme and RADPROM project funded by Italian Space Agency (ASI). In 2019 he co-founded BlackCat Beyond as a start-up company focusing on silicon dosimeters for medical and space applications. He is IEEE Senior Member.
- On-Chip Infrastructure for Mission-Mode Monitoring of Resilient Systems: Towards Silicon Lifecycle Management, Fabian Vargas
Abstract: Simulation and laboratory measurements can never tell the whole story of how devices will behave in real-world use. In real world, various interferences can occur simultaneously, where the IC can be exposed, for instance, to extreme environmental temperatures, battery wear-out/instability, electromagnetic interference (EMI), ionizing radiation (TID, SEEs) and aging (BTI, HCI, TDDB, electromigration). Moreover, there are many standards used to certify electronic circuits & systems, but they are applied independently (on fresh devices), not considering the combined effects one phenomenon may take over the other. In this always-challenging context, this talk gives us an insight on how IHP addresses the design of ICs through the use of on-chip cross-layer infrastructure, and how we can enable a range of new (in-field) optimizations throughout the lifecycle of the circuits. Such infrastructure deals with sensors to detect SEU in memory elements and SET in logic, monitoring power-supply activity, temperature, measuring electronics aging and tracking in-field real-time circuit speed performance degradation during IC lifetime. Other types of monitors (watch-dogs) aim to guarantee mixed-criticality task execution in real-time operating system (RTOS). Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std. This on-chip infrastructure is being implemented in different versions of a RISC-V processor, and manufactured with the IHP’s BiCMOS 130nm rad-hard technology. This solution enables mission-mode monitoring of IC operation, which is a critical aspect of silicon lifecycle management (SLM) framework.
Bio: Fabian Vargas obtained the Ph.D. Degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. At present, he is Senior Scientist at IHP – Leibniz Institute for High Performance Microelectronics, Germany, where he works on the design of on-chip sensors and cross-layer resilience for aerospace systems. Vargas has served as Technical Committee Member and Guest-Editor in many IEEE-sponsored conferences and journals. He holds several patents and published over 200 refereed papers. Vargas was researcher of the BR National Science Foundation from 1996 to 2023. He co-founded the IEEE-Computer Society Latin American Test Technology Technical Council (IEEE LA-TTTC) in 1997 and the IEEE Latin American Test Symposium (LATS) in 2000. He received the Meritorious Service Award of the IEEE Computer Society for providing significant services as chair of these groups. Vargas is Golden Core Member of the IEEE Computer Society and Senior Member of the IEEE.
- Matrix Radiation Sensors in a standard CMOS technology, Yakov Roizin
Abstract: Ionizing radiation sensing devices based on the floating gate (FG) principle and methods of their operation are discussed in the talk. The focus is on the novel sensors comprising two identical arrays of single Poly FG cells with integrated low-capacitance ionization chambers, where each cell in one array has a counterpart in the other array. The cells from two arrays are connected into logical diferential pairs. The device is programmed before sensing and does not need a power supply in the registation mode. For ultra-low dose measurements or registration of single effects, the number of logical pairs influenced by radiation is evaluated. Special algorithms are used to mitigate the influence of retention effects, read disturbs and noises of the single cells. For large doses, the mean threshold voltage shifts are used as a measure of the absorbed dose. The exemplary 256×256 array prototypes fabricated in a standard 180nm 5V CMOS flow (die size 6.5mm x 6.5mm) allowed detectable doses of gamma and X-ray radiation down to 100 microGray.
Bio: Yakov Roizin is the Chief Scientist and Fellow of Tower Semiconductor. He has been working for the company for the last 27 years developing scaled down CMOS technologies with embedded sensors and non-volatile memories. Yakov received his Ph.D. and D.Sc.(Hab) degrees from the leading academic institutions of the former USSR. Dr. Roizin is the author of more than 350 publications, including 80 patents. Yakov is a full visiting professor of Technion-Israeli Institute of Technology and Tel Aviv University.
- Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments, Philip Neudeck
Abstract: This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1,2], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [3], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [4]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages [5]. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, the majority of processing steps necessary to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.
[1] P. Neudeck et al., Proc. 2018 IMAPS Int. Conf. High Temperature Electronics, 71.
[2] L. Chen et al., Proc. 2016 IMAPS Int. Conf. High Temperature Electronics, 66.
[3] P. Neudeck, et al., IEEE J. Electron Devices Soc. 7, 100, 2018.
[4] J. Lauenstein, et al., 2019 IEEE Radiation Effects Data Workshop, DOI: 10.1109/REDW.2019.8906528
[5] P. Neudeck et al., Materials Science Forum 963, 813, 2019.
Bio: Philip G. Neudeck received the B.S. (with distinction), M.S., and Ph.D. degrees in electrical engineering from Purdue University, West Lafayette, Indiana USA, in 1986, 1987, and 1991, respectively. In 1991, he became the lead semiconductor device engineer of the silicon carbide (SiC) sensors and electronics research team at NASA Lewis Research Center, which was renamed to NASA Glenn Research Center in 1999. He has overseen the design, modeling, fabrication, and electrical characterization of prototype SiC electronic devices being developed for high-temperature or high-power operation in aerospace-related systems. His most notable early contributions to the SiC electronics field include the first demonstration of multi-kilovolt SiC rectifiers and identification of micropipes as crystal defects that limit the performance of SiC power devices, as well as pioneering contributions to SiC homo-epilayer and hetero-epilayer growth. Dr. Neudeck is presently focusing on development of increasingly capable SiC extreme environment durable integrated circuit (IC) electronics technology, including first demonstrations of stable semiconductor IC operation for more than a year at 500 °C. Dr. Neudeck is a Fellow of the IEEE, and was honored by IEEE-USA as the recipient of the 2019 Harry Diamond Memorial Award for distinguished technical contributions in the field of electrotechnology while in U.S. Government service.
- ESA programs and standards for ASIC, FPGA and IP Cores for space, Agustín Fernández León
Abstract: ESA has recently led a major update of the ECSS standard applied for the development of ASIC, FPGA and IP Cores that are used in ESA spacecraft. Two new complementary standards, one centred in engineering requirements and second one addressing product assurance were as a result published in October of 2023 and are since then applicable. I will walk the audience through the main contents and requirements laid our in the engineering standard- This standard makes reference to an ECSS handbook available since 2016 that explains a large number of techniques that can be applied, at various levels of the IC development, to mitigate the effects of radiation on ICs. A brief walk through this handbook will also be presented. Lastly, I will conclude with a short summary of the most recent developments that ESA is engaged in in order to make the next generations of radiation hardened ultra-deep submicron (28, 22 and 7 nm ) technology and European devices available.
Bio: Agustín Fernández León works as Lead Microelectronics Engineer at the European Space Agency (ESA) in the European Space Research and Technology Centre (ESTEC), The Netherlands. He has worked 24 years at ESA, 20 of them as Head of the Microelectronics section, providing technical support to ESA missions in the area of ASICs, FPGA and IP Cores design and technology. Before joining ESA, Agustín worked 9 years in Alcatel, Madrid, as digital ASIC designer for telecom wireline applications. He has a MSc in Microelectronics by North Carolina State University and a BSc in Physics by Universidad Complutense de Madrid.