IEEE Solid-State Circuits Society

IEEE Solid-State Circuits Society IEEE Solid-State Circuits Society

2023 SSCS Student Circuit Contest

Open to both Undergraduate and Graduate Students

  • The goal of this challenge is to design an integrated circuit by using the greatest number of components picked from the provided list (no other components should be used except the ones in the provided list).  
  • The circuit does not have to be original and/or optimized, although a proper functionality is expected (e.g. an amplifier has to amplify,  an oscillator has to oscillate, etc…)
  • Beside the number of components used, the evaluation committee will judge the rationale of the solution proposed and the circuit characterization (i.e. simulation provided).
  • The circuit can be implemented in any regular CMOS technology available to you. (Please state the technology adopted in your the submission and how this affected your design) 

Some rules must be followed:

• The circuit must have one ground (GND) and one voltage supply (VDD) compatible with the technology you use

• Each component in the list can be used only once

• The use of each component must be necessary for the proper functionality of the circuit (e.g. no dummies components)

• The circuit must have at least an identified output 

• Component parameters specified in the provided list cannot be changed (more parameters will depend on the technology you use such as Cox, mobility, voltage threshold, supply voltage,  etc..).

• The circuit must be simulated, and simulation results must be provided to demonstrate the desired functionality. 


List of components:

Ideal input voltage source: 
• Ideal current source (100uA)
• GND net 
• VDD net connected to a supply
- 1 output 
- 2 NMOS transistor with (W/L)=100/1
- 1 NMOS transistor with (W/L)=50/1
- 1 NMOS transistor with arbitrary (W/L)
- 2 capacitors (ideal) of 1pF
- 2 inductors (arbitrary values between 100pH and 10nH) but with a quality factor equal to 10 @ 2GHz * 
- Jolly: the two inductors could be coupled with a coupling factor k=0.9  

* the quality factor of 10 must be modelled with a resistance R in series with the inductor L such that R=6.28x2e8xL Ohm

 

Submission Instructions and Deadlines:

  • You must be an undergraduate or graduate student currently enrolled in a college or university to enter the contest. You do not have to be an SSCS member to submit to the contest, however, you must be an IEEE member. 
  • Please read the Contest Rules and Regulations here.
  • Please download the template (PDF Format) to explain your answer. 
  • Your answer must be no more than two-pages in the IEEE paper style.
  • Upload your answer here and fill out the submission form
  • DEADLINE FOR SUBMISSIONS: JULY 31st, 2023. 

 

Awards

Up to three contestants with the best answers will receive US$2K each towards attending an SSCS-sponsored conference (ISSCC, CICC, ESSCIRC, VLSI Symp., ASSC). This award is paid either as a reimbursement following the attended conference or will be paid directly to the conference for registration and to the hotel for accommodations. All the submitters with the right answers will receive one year of free membership in the Solid-State Circuits Society, and their names will be highlighted in the Solid-State Circuits Magazine.

 

Questions:

If you have any questions regarding the contest, please email sscs-staff@ieee.org