IEEE Solid-State Circuits Letters

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology 150 150

Abstract:

Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various …

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A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications 150 150

Abstract:

This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18- $\mu $ m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the …

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An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference

An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference 150 150

Abstract:

This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to …

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A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue

A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue 150 150

Abstract:

This letter presents an 8-channel current-mode stimulator achieving a ±10.2 V voltage compliance in a standard CMOS process, supporting up to 4.5 mA stimulation current per channel. The proposed dynamic charge pump (DCP), which adaptively sizes its switches based on the stimulation current, helps achieve ~15% higher power efficiency at low currents compared …

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A Cryo-CMOS Smart Temperature Sensor for the Ultrawide Temperature Range From 5 K to 296 K

A Cryo-CMOS Smart Temperature Sensor for the Ultrawide Temperature Range From 5 K to 296 K 150 150

Abstract:

This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves …

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A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths

A 0.015-mm2 0.5-V Synthesizable Hybrid PLL With Multi-Phase Linear Proportional-Gain Paths 150 150

Abstract:

This brief presents a 0.015-mm2 0.5-V synthesizable hybrid phase locked loop (PLL). All blocks including an analog proportional-gain path can be logically or physically synthesized with digital cells and hardware languages. To mitigate the mismatch and common-mode fluctuation problems of a voltage-mode phase detector, multi-phase proportional-gain paths are designed for …

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A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks

A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks 150 150

Abstract:

This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard $\pi $ -type equivalent circuits often suffer from bandwidth degradation due to …

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220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS

220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS 150 150

Abstract:

This letter presents a broadband $G$ -band power amplifier (PA) designed in a 130-nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor technology. Unlike dual-band matching and staggered tuning techniques to obtain large operation bandwidth (BW), we propose a common broadband amplification stage in this work for its flexibility. In each stage, inductive …

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Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles

Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles 150 150

Abstract:

Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this …

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