IEEE Solid-State Circuits Letters

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications

Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications 150 150
Author(s): Po-Han Chen, Bo Wun Cheng, Michael Oduoza, Zhouhua Xie, Rupert Lu, Sai Gautham Ravipati, Kalhan Koul, Alex Carsello, Yuchen Mei, Mark Horowitz, Priyanka Raina

Abstract:

Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous …

Published in: IEEE Solid-State Circuits Letters
Page(s): 293 – 296
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3613245
Publisher: IEEE

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A Battery-Free BLE Backscatter Communication Chip for Wearable Systems

A Battery-Free BLE Backscatter Communication Chip for Wearable Systems 150 150
Author(s): Yongling Zhang, Ji Xiong, Junzai Chen, Xiaoyu Li, Jinrui Zuo, Yan Wang, Xiaoyi Wang, Miao Meng

Abstract:

This letter presents a backscatter chip that features bidirectional communication with commodity bluetooth low-energy (BLE) transceivers. For uplink, the chip reflects a reverse-whitened BLE tone into single-sideband (SSB) GFSK-modulated BLE packets via a proposed replica VCO-based GFSK modulator and an inductor-free SSB reflector. For downlink, the BLE packets are frequency …

Published in: IEEE Solid-State Circuits Letters
Page(s): 297 – 300
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3612423
Publisher: IEEE

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A Fully-Dynamic Capacitive Touch Sensor With Tri-level Energy Recycling and Compressive Sensing Technique

A Fully-Dynamic Capacitive Touch Sensor With Tri-level Energy Recycling and Compressive Sensing Technique 150 150
Author(s): Xiangdong Feng, Zhiyu Wang, Haoyang Li, Jiaqing Li, Wei-Chin Lin, Xin Hu, Zhong Tang, Yuyan Liu, Qinwen Fan, Yuxuan Luo, Bo Zhao

Abstract:

Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3612093
Publisher: IEEE

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A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants

A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 150 150
Author(s): Ronald Wijermars, Yi-Han Ou-Yang, Sijun Du, Dante G. Muratore

Abstract:

This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm …

Published in: IEEE Solid-State Circuits Letters
Page(s): 305 – 308
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3611484
Publisher: IEEE

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A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter

A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter 150 150
Author(s): David Dolt, Samuel Palermo

Abstract:

This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple …

Published in: IEEE Solid-State Circuits Letters
Page(s): 285 – 288
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3610901
Publisher: IEEE

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A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication

A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication 150 150
Author(s): Lucrezia Navarin, Karl Norling, Marco Parenzan, Stefano Ruzzu, Andrea Neviani, Andrea Bevilacqua

Abstract:

A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 289 – 292
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3611018
Publisher: IEEE

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A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation

A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation 150 150
Author(s): Kai Cui, Honglei Xu, Yingduo Duan, Yan Lu, Xiaoya Fan, Yanzhao Ma

Abstract:

This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 261 – 264
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608096
Publisher: IEEE

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A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 150 150
Author(s): Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim

Abstract:

This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw …

Published in: IEEE Solid-State Circuits Letters
Page(s): 265 – 268
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608187
Publisher: IEEE

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