Presents corrections to the paper, (Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications).
This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…
This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by $4\times $ compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier …
This letter presents a multiband fully integrated ultralow-power (ULP) transceiver with a two-step wake-up receiver (WuRX) and switched-capacitor (SC)-based high-efficiency transmitter. Operating from 200 MHz to 1 GHz, the transceiver covers most IoT applications on a single chip. By employing a novel two-step wake-up scheme with a rotating correlator, the proposed …
This letter presents a multimode readout IC for 6.5-in 34Tx/16Rx on-cell touch AMOLED (OCTA) panels, detecting both conductive and nonconductive objects (NCos) without panel modifications. To enable this dual detection, a reconfigurable analog front-end (AFE) is proposed, functioning as either a capacitance-to-voltage converter or a triboelectric charge sampler. In …
Miniaturized biomedical implants are currently constrained by limited wireless power transfer (WPT) efficiency under load variation and spatial misalignment. This work presents a custom magnetoelectric (ME) power link incorporating a load-adaptive CMOS rectifier to address these challenges. By employing a current sensing control loop for dynamic switch sizing and delay …
This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. …
This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline …
This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive …
