IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

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3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems

3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems 150 150
Author(s): Arya Upadhyay

Abstract:

Moving sensor data and neural-network operands through conventional external-memory hierarchies can constitute a substantial fraction of the energy required for edge inference. Motivated by a three-tier near-sensor organization, this work evaluates memory localization using a controlled architecture-level study and an independent transistor-level communication-link analysis. Five convolution configurations are evaluated on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3735890
Publisher: IEEE

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Self-Heating and Parasitic Effects in Multi-Tier CFET Design

Self-Heating and Parasitic Effects in Multi-Tier CFET Design 150 150
Author(s): Sufia Shahin, Mahdi Benkhelifa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 153 – 158
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704373
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 135 – 143
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704358
Publisher: IEEE

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Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning

Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning 150 150
Author(s): M. Drouhin, M. Grelier, M. Deroo, Y. Sassi, E. Monteblanco, N. Davila, G. Mihajlović, R. V. Chopdekar, T. S. Santos, J. A. Katine, D. Ravelosona

Abstract:

Artificial neural networks (ANNs) have enabled major advances in artificial intelligence, yet their growing computational and energy demands challenge conventional von Neumann architectures due to the costly separation of memory and processing. In-memory computing has emerged as a promising solution, particularly through memristive crossbar arrays capable of performing multiply-and-accumulate operations …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 129 – 134
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3702001
Publisher: IEEE

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P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments

P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments 150 150
Author(s): Christian Duffee, Jordan Athas, Igor Kadota, Randall Berry, Pedram Khalili Amiri

Abstract:

The frequency assignment problem is a nondeterministic polynomial-time hard (NP-hard) optimization problem concerning the assignment of frequency channels to wireless transmitters. Typically, the aim is to minimize interference between transmitters while maintaining a high level of service. In this work, the use of probabilistic d-dimensional bits, or p-dits, for this …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 78 – 85
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690563
Publisher: IEEE

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1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing

1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing 150 150
Author(s): Md Yasir Bashir, Lalith Adithya Sai C., Shubham Sahay

Abstract:

Reservoir computing (RC), a computational paradigm inspired by the recurrent neural networks (RNNs), offers a promising framework for efficient temporal processing with minimal training overhead. Hardware implementation of RC primitive requires devices that exhibit short-term memory, nonlinearity, and energy-efficient state-switching dynamics. While emerging nonvolatile memory (eNVM) technologies have been explored …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 120 – 128
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690766
Publisher: IEEE

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Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture

Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture 150 150
Author(s): Yashvardhan Singh, Siddharth Penumatsa, Prashanth Barla

Abstract:

Spin-transfer torque magnetic tunnel junction (STT-MTJ) is widely recognized as a promising device for computation-in-memory (CIM) architecture due to its advantages, such as simple nonvolatile structure, CMOS compatibility, and scalability. In spite of the advantages, achieving reliable and efficient sensing of STT-MTJ remains a design challenge. This work presents a …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 95 – 103
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690460
Publisher: IEEE

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A CMOS Probabilistic Computing Chip With Hardware-Aware Learning

A CMOS Probabilistic Computing Chip With Hardware-Aware Learning 150 150
Author(s): Jinesh Jhonsa, William Whitehead, Yihao Wu, David Mccarthy, Shuvro Chowdhury, Kerem Y. Camsari, Luke Theogarajan

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 86 – 94
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3689506
Publisher: IEEE

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