IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150
Author(s): Chaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 199 – 204
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 192 – 198
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits

QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits 150 150
Author(s): Mohan Raj Manoharan

Abstract:

Wearable AI workloads such as sensor fusion, physiological inference and uncertainty quantification are probabilistic, yet the neural processing units that serve them are deterministic matrix-multiply engines that discard distributional information at every layer. We describe QEPC, a deferred-evaluation execution model in which probability mass functions are maintained in non-volatile state …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740368
Publisher: IEEE

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Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing

Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing 150 150
Author(s): Sandeep Semwal, Pin Su

Abstract:

The growing demand for energy-efficient computing has intensified interest in highly scalable device technologies such as complementary field-effect transistors (CFETs). In this work, we investigate S-curve engineering for a unique ferroelectric-on-top (FE-o-T) negative-capacitance (NC) CFET through calibrated numerical simulations to assess its potential for ultra-low-power computing and supply-voltage scaling. Our …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740342
Publisher: IEEE

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A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction

A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction 150 150
Author(s): Supriyo Bandyopadhyay

Abstract:

The xor Boolean logic gate is widely used in many applications such as encryption (xor ciphers), binary addition (half- and full-adders), error detection (parity bits), etc., but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 185 – 191
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3719208
Publisher: IEEE

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A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration

A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration 150 150
Author(s): Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu

Abstract:

Conventional large language models (LLMs) have large parameter sets, making inference costly and energy-intensive; mixture-of-experts (MoEs) mitigates this by activating fewer weights per token, but fine-grained MoE LLMs still face runtime workload variability, inefficient conventional scheduling, and high bandwidth memory (HBM) loading energy/bandwidth demands. A3D-MoE addresses these with 3…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 176 – 184
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3713957
Publisher: IEEE

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Defect-Engineered Mn-Doped ZnO Memristors for Hardware-Aware Neuromorphic Image Classification

Defect-Engineered Mn-Doped ZnO Memristors for Hardware-Aware Neuromorphic Image Classification 150 150
Author(s): Richa Bharti, Lipika Sasmal, Shrestha Chaturvedi, Ajay D. Thakur

Abstract:

The practical deployment of neuromorphic hardware requires active materials with precisely controlled defect dynamics to govern charge transport and synaptic plasticity. While pristine ZnO offers a structurally favorable switching platform, the stochastic distribution of native defects often results in poor switching uniformity and compromised retention. In this study, we utilize …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3736551
Publisher: IEEE

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Probabilistic Computing With Neuromorphic Elements

Probabilistic Computing With Neuromorphic Elements 150 150
Author(s): Zonglong Li, Laurie E. Calvet

Abstract:

This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 167 – 175
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3712198
Publisher: IEEE

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Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 159 – 166
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

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