JSSC Best Paper Award

Best Paper of 2024

8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter

Cooper S. Levy ; Zhe Xuan ; Jahnavi Sharma ; Duanni Huang ; Ranjeet Kumar ; Chaoxuan Ma ; Songtao Liu ; Jinyong Kim ; Xinru Wu ; Tolga Acikalin ; Haisheng Rong ; Ganesh Balamurugan ; James E. Jaussi

IEEE Journal of Solid-State Circuits ( Volume: 59, Issue: 3, March 2024)

10.1109/JSSC.2023.3344072

Cooper S. Levy

Intel Labs
Hillsboro, OR, USA

Zhe Xuan

Intel Labs
Hillsboro, OR, USA

Jahnavi Sharma

Intel Labs
Hillsboro, OR, USA

Duanni Huang

Intel Labs
Santa Clara, CA, USA

Ranjeet Kumar

Intel Labs
Santa Clara, CA, USA

Chaoxuan Ma

Intel Labs
Santa Clara, CA, USA

Songtao Liu

Intel Labs
Santa Clara, CA, USA

Jinyong Kim

Intel Labs
Hillsboro, OR, USA

Xinru Wu

Intel Labs
Santa Clara, CA, USA

Tolga Acikalin

Intel Labs
Santa Clara, CA, USA

Haisheng Rong

Intel Labs
Santa Clara, CA, USA

Ganesh Balamurugan

Intel Labs
Hillsboro, OR, USA

James E. Jaussi

Intel Labs
Hillsboro, OR, USA

The IEEE Journal of Solid-State Circuits (JSSC) Best Paper Award recognizes the most outstanding paper published in the IEEE Journal of Solid-State Circuits during the previous calendar year. This award highlights exceptional contributions that advance the state of the art in integrated circuit (IC) design through technical excellence, clarity, and long-term impact on the field.

Award Description

This annual award honors the authors of the most distinguished paper published in JSSC. The winning paper is selected through a rigorous, multi-stage review and voting process involving the Journal’s editorial leadership and reviewers.

Prize

  • Single annual award, with multiple recipients permitted
  • US$300 per author, up to a total of US$4,500
  • If the paper has more than 15 authors, the US$4,500 total is divided equally
  • Each recipient also receives an official certificate

Funding:

The award is fully funded by the IEEE Solid-State Circuits Society (SSCS).

Eligibility

  • All papers published in the IEEE Journal of Solid-State Circuits during the previous year
  • Self-nominations are not permitted
  • Nominations within the same institution are not permitted

Nomination Process

Nominations are gathered from:

  • Associate Editors and Guest Editors who handled the paper
  • Peer reviewers, who may nominate a paper during the review process
  • Citation data and IEEE Xplore download metrics are provided to editors to support nomination decisions

A short supporting statement (a few sentences) is required for each nomination.

Multiple nominations for the same paper are allowed and serve as evidence of its impact and strength.

After nominations close, the final published papers are distributed to the selection committee for evaluation.

Selection Committee

The committee is appointed by the Editor-in-Chief (EiC) and consists of:

  • The two most recent JSSC Editors-in-Chief (serving 6-year staggered terms)
  • Six current Associate Editors, selected to ensure broad technical coverage and a balance of industry and academic perspectives
  • The current EiC, who serves as a non-voting chair (votes only to break ties)

Committee procedures:

  • Work is conducted individually; no in-person meetings
  • Votes are submitted by email
  • A quorum is reached with >50% of voting members

Voting Method:

Each committee member ranks their top three papers:

  • 1st place = 3 points
  • 2nd place = 2 points
  • 3rd place = 1 point

The paper with the highest total score is selected as the winner.

Ties are resolved by the EiC.

The EiC forwards the final selection to IEEE following approval from the SSCS Vice President of Publications.

Schedule

  • September 1 – October 1: Nomination period
  • October 1 – November 30: Committee review and final selection
  • December: Winners notified
  • February: Award presented at the IEEE International Solid-State Circuits Conference (ISSCC)

Basis for Judging

The selection committee evaluates papers based on:

  • Impact on the field (current and potential future influence)
  • Technical excellence and rigor
  • Novelty and innovation
  • Clarity of presentation and writing

Presentation & Publicity

The award is presented each year at the IEEE International Solid-State Circuits Conference (ISSCC).

Winners are featured in:

  • IEEE Solid-State Circuits Magazine (SSC-M)
  • SSCS website
  • Additional SSCS communications and promotions

Past Recipients

YearRecipientsTitleVolume/Issue
2023Emir Ali Karahan, Zheng Liu, and Kaushik SenguptaDeep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power AmplifiersVol. 58, Issue 11, Page(s): 3074-3088, November 2023
2022Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen C. Au, Sraavan R. Mundlapudi, Kejian Shi, and Weiyu LengA Harmonic-Mixing PLL Architecture for Millimeter-Wave ApplicationVol. 57, Issue 12, Page(s): 3552-3566, December 2022
2021Hao Li, Ganesh Balamurugan, Taehwan Kim, Meer N. Sakib, Ranjeet Kumar, Haisheng Rong, James Jaussi, and Bryan CasperA 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal ControlVol. 56, Issue 1, Page(s): 19 – 29
2020Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, and Brucek KhailanyA 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nmVol. 55, Issue 4, Page(s): 920 – 932
2019Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James Jaussi, and Bryan CasperA 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMOVol. 54, Issue 12, Page(s): 3565 – 3576
2018Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takayuki Ezaki, and Teruo Hirayama.A 6.9-μm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel- Parallel 14-Bit Subthreshold ADCVol. 53, Issue 11, Page(s): 3017 – 3025
2017Bodhisatwa Sadhu, Yahya Tousi,  Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Örjan Renström, Kristoffer Sjögren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Mark Ferriss, Duixian Liu, Daniel Friedman, and Alberto Valdes-GarciaA 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G CommunicationsVol. 52, Issue 12, Page(s): 3373 – 3391
2016Lucien Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, and Gerard LassacheA 2.2 GHz Continuous-Time ΔΣADC With −102 dBc THD and 25 MHz BandwidthVol. 51, Issue 12, Page(s): 2906 – 2916
2015Tzu-Chien Hsueh, Frank O’Mahony, Mozghan Mansuri, and Bryan CasperAn On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum MeasurementsVol. 50, Issue 7, Page(s): 1711 – 1721
2014Michael Boers, Bagher Afshar, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bevin George Perumana, Theodoros Chalvatzis, Spyros Kavvadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Jesus A. Castaneda, Tirdad Sowlati, Maryam Rofougaran, and Ahmadreza Rofougaran.A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization DiversityVol. 49, Issue 12, Page(s): 3031 – 3045
2013Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, and Haiyang ZhuA 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 mm CMOSVol. 48, Issue 12, Page(s): 3059-3066, December. 2013
2012David Murphy, Hooman Darabi, Asad Abidi, Amr Amin Hafez, Ahmad Mirzael, Mohyee Mikhemar, and Mau-Chung Frank ChangA Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless ApplicationsVol. 47, Issue 12, Page(s): 2943 – 2963, December 2012
2011Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, and Kofi A. A. MakinwaA 4-GHz Continuous-Time Δ-ΣADC with 70-dB DR and -74 dBFS THD in 125-MHz BWVol. 46, Issue 12, Page(s): 2857 – 2868, December 2011
2010Christopher Peter Hurrell, Colin Lyden, David Laing, Derek Hummerston, and Mark VickeryAn 18 b 12.5 MS/s ADC With 93 dB SNRVol. 45, Issue 12, Page(s): 2647 – 2654, December 2010
2009Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. FriedmanA 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOSVol. 44, Issue 12, Page(s): 3526 – 3538, December 2009
2008Junghwan Han and Ranjit GharpureyRecursive Receiver Down-Converters With Multiband Feedback and Gain-ReuseVol. 43, Issue 5, Page(s): 1119 – 1131, May 2008
2007John Poulton, Robert Palmer, Andrew Fuller, Trey Greer, John Eyles, William Dally, and Mark HorowitzA 14-mW 6.25-Gb/s Transceiver in 90-nm CMOSVol. 42, Issue: 12, Page(s): 2745 – 2757, December 2007
2006Jonathan B. Ashbrook, Hyeon-Min Bae, Sanjiv Chopra, Jinki Park, Naresh R. Shanbhag, and Andrew C. SingerAn MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links DigitalVol. 41, Issue: 11, Page(s): 2541 – 2554, November 2006
2005Drs. Michiel. A. P. Pertijs, Kofi A. A. Makinwa and Johan H. HuijsingA CMOS smart temperature sensor with a 3s inaccuracy of + 0.1° C from -55° C to 125° CVol. 40, Issue: 12, Page(s): 2805 – 2815, December 2005
2004Xiang Guan, Hossein Hashemi, and Ali HajimiriA Fully Integrated 24-GHz Eight-Element Phased-Array Receiver in SiliconVol. 39, Issue: 12, Page(s): 2311 – 2320, December 2004
2003Danilo Manstretta, Brandolini Massimo, and Francesco SveltoSecond-order intermodulation mechanisms in CMOS downconvertersVol. 38, Issue: 3, Page(s): 394 – 406, March 2003
2002Alireza Shirvani, David K. Su, and Bruce A. WooleyA CMOS RF power amplifier with parallel amplification for efficient power controlVol. 37, Issue: 6, Page(s): 684 – 693, June 2002
2001Marko Sokolich, Charles H.Fields, Stephen Thomas III, Binqiang Shi, Young Kim Boegeman, Mary Montes, Rosanna Martinez, Allan R. Kramer, and Meena MadhavA low-power 72.8-GHz Static Frequency Divider in AlInAs/InGaAs HBT TechnologyVol. 36, Page(s): 1328 – 1333, September 2001
2000Ichiro Fujimori, Akihiko Nogi, and Tetsuro SugimotoA Multibit Delta–Sigma Audio DAC with 120-dB Dynamic RangeVol. 35, Page(s): 1066 – 1073, August 2000
1999Brian P. Brandt and Joseph LutskyA 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at NyquistVol. 34, Page(s): 1788 – 1795, December 1999.
1998Mark. J. Loinaz, K. J. Singh, Andrew. J. Blanksby, David A. Inglis, Kamran. Azadet, and Bryan AcklandA 200-mW, 3.3-V, CMOS Color Camera IC Producing 352 × 288 24-b Video at 30 Frames/sVol. 33, Page(s): 2092 – 2103, December 1998.
1997Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, and Stephen W. HarstonA cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNRVol. 32, Page(s): 1896 – 1906, December 1997.
1996Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John M. Drynan, MasahirKomuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko Ichinose, Tomoo Imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, and Takashi OkudaA 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror DelayVol. 31, Page(s): 1656- 1668, November 1996
1995Loke Kun Tan and Henry SamueliA 200 Mhz Quadrature Digital Synthesizer/Mixer in 0.8 mm C.M.O.S.Vol. 30, Page(s): 193-200, March 1995
1993Michiel de Wit, Khen-San Tan, and Richard K. Hester Low-Power 12b Analog-to-Digital Converter with On-Chip Precision TrimmingVol. 28, Page(s): 455 – 461, April 1993
1992Masato Motomura, Hachiro Yamada, Tadayoshi EnomotoA 2K-Word Dictionary Search Processor (DISP) LSI with an Approximate Word Search CapabilityVol. 27, Page(s): 883 – 891, June 1992
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