TC-OSE Committee Members

Mehdi Saligane is a Research Scientist in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received his M.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016, respectively. He worked at STMicroelectronics, in France, as a Research Engineer from 2010 to 2015, and after completing his Ph.D., he joined the Michigan Integrated Circuits Lab at the University of Michigan. Dr. Saligane’s current research interests are in low-power and energy-efficient IC design, with a focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the Analog Working Group, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem.

Tim ‘Mithro’ Ansell is a pioneering figure in open-source silicon, known for his crucial role in democratizing chip design. Through initiatives like the SkyWater and GlobalFoundries open-source PDKs and the Open MPW program, he has significantly lowered barriers to entry, enabling innovation and access for individuals and smaller entities in semiconductor technology.

In 2013, Mitch left Hitachi and rewrote the system, now known as CVC-RV (Circuit Validity Check – Reliability Verification), as open-source. As a consultant, he currently leverages CVC-RV for full-chip verification of SOC and DRAM designs. Additionally, Mitch collaborates with Efabless to facilitate full-chip device-level LVS verification using open source tools.

Mitch’s career has been marked by a commitment to advancing reliability verification methodologies and contributing to the open-source community.

Tim Edwards is director of analog at Efabless corporation. He has been an advocate of open source hardware and the open source tools to create it since the early 1990s.  He developes and maintains the EDA software magic, netgen, xcircuit, IRSIM, qflow, CACE, and others, and regularly contributes to open source EDA tool and open PDK development.  He helped develop the first open-source PDK from SkyWater, the Efabless open MPW shuttle run, and the Efabless Caravel harness chip.  He spends much of his time on Slack helping designers get their open source chip designs done.

Saptarshi Ghosh is a Postdoctoral Researcher at the Institute of Neuroinformatics  (INI), a joint institute of the University of Zürich and ETH Zürich in Switzerland. Earlier, He was a postdoc researcher at the Kavli Institute for Systems Neuroscience, Norwegian University of Science and Technology (NTNU), in Norway. He received his M.Sc. and PhD in Physics from the Indian Institute of Technology in Kanpur and Indore, respectively. His research interests include developing hardware-aware spiking neural models for NeuroAI, optimized for implementation on ultra-low-power neuromorphic hardware with a focus on biomedical applications. He is a big proponent of INI’s mission “to discover the key principles by which brains work and to implement these in artificial systems that interact intelligently with the real world”.

Gregory Kielian leads a multidisciplinary team at Google Research, where he focuses on bridging the gap between large language models (LLMs) and resource-constrained edge hardware. His group explores hardware-software co-design of novel ML architectures, efficient algorithms, transformer-training techniques, and EdgeLLM ASIC solutions. By enabling LLMs to operate locally on edge devices, his team aims to unlock real-time interaction with locally-intelligent machines.

He received his Bachelor’s degree in Physics from the University of California, Berkeley. His research and publications span LLM efficiency and augmenting hardware design with LLMs and reinforcement learning (RL) techniques. Beyond his work at Google, Gregory participates in community outreach, teaching Linux and AI to foster innovation and expand access to technology.

Kwantae Kim received the B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2015, 2017, and 2021, respectively. From 2015 to 2017, he was with the Healthrian R&D Center, Daejeon, where he designed bio-potential readout IC for mobile healthcare solutions. In 2020, he was a Visiting Student with the Institute of Neuroinformatics, University of Zürich and ETH Zürich, Zürich, Switzerland, where he has been a Post-Doctoral Researcher since 2021. His research interests include analog/mixed-signal ICs for time-domain processing, in-memory computing, bio-impedance sensor, and neuromorphic audio sensor.

Peter Kinget is the Bernard J. Lechner Professor of Electrical Engineering at Columbia University in New York. His research group focusses on the design of analog and RF integrated circuits and the novel systems or applications they enable in communications, sensing, computing, and power management. He also devotes a lot of his energy to teaching initiatives like https://mosbius.org and https://vlsidesignlab.org He received his engineering and Ph.D. degrees in electrical engineering from the Katholieke Universiteit in Leuven (Belgium). He has worked in industrial research and development at Bell Laboratories, Broadcom, Celight and Multilink before joining the faculty of the Department of Electrical Engineering, Columbia University, NY in 2002. He served as Department Chair from 2017 to 2020. He is also a consulting expert on patent litigation and a technical consultant to industry. Peter is a Fellow of the IEEE and is widely published. He received several awards including the “IEEE Solid-State Circuits Society 2020 Innovative Education Award and the “2011 IEEE Communications Society Award for Advances in Communication” (for an outstanding paper in any IEEE Communications Society publication in the past 15 years). He is a “Distinguished Lecturer” for the IEEE Solid-State Circuits Society (SSCS), and has been an Associate Editor of the IEEE Journal of Solid State Circuits (2003-2007) and the IEEE Transactions on Circuits and Systems II (2008-2009). He has served on the program committees of many of the major solid-state circuits conferences and has been an elected member of the IEEE SSCS Adcom (2011-2013 & 2014-2016).

Juan Sebastian Moya-Baquero, works as a mixed-signal designer at Symbiotic EDA. He conducted research at the MICL at the University of Michigan during 2024. His research interests include circuit and architectural techniques for clock generation in systems-on-a-chip (SoC), wired and wireless analog frontends, inductive links, oscillators, and low-power analog circuits. He received his Ph.D. in Electronics Engineering from Universidad Industrial de Santander, Bucaramanga, Colombia, his M.Sc. in Electrical Engineering from Universidade Federal de Santa Catarina, Florianopolis, Brasil, and his B.E. in Electrical and Electronics from Universidad de Los Andes, Colombia. He has experience taping out in both sky130 and gf180mcu open source PDKs. He works to increase the number of undergraduate and graduate students in integrated devices and circuits.

Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for embedded machine learning. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society, as well as the Data Converter Subcommittee Chair and the Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He is the founding faculty co-director of the Stanford SystemX Alliance and the faculty director of Stanford’s System Prototyping Facility (SPF). He is a Fellow of the IEEE.

Jun-ichi Okamura is a seasoned entrepreneur in the semiconductor sector with over 38 years of IC design experience. Jun is an inventor and co-inventor, holding over 30 US patents.

1986 Jun began his career as Toshiba’s leading DRAM memory designer. Later, he contributed his expertise to IBM in Burlington, VT.

1999, he joined THine Electronics, a Japanese semiconductor startup, as a key business executive.

In 2006, Jun founded Trigence Semiconductor, which received its first investment in 2012 from Intel Capital due to the potential of its unique Dnote® audio technology. Despite accumulating 22M USD, Trigence faced challenges during a Series-D funding round amid the China-USA trade war and COVID-19. Thus, it was regally liquidated in March 2022.

In 2023, Jun joined AIST Solutions, contributing his wealth of experience. Since then, Jun has been actively involved in Open-Source Silicon for Japan and established the non-profit OpenSUSI (Open Source Utilized Silicon Initiatives) in 2024.

IEEE senior member since 2021

Harald Pretl (S’97-M’01-SM’08) was born in Linz, Austria, in 1972. He received a Dipl.-Ing. degree in electrical engineering from the Graz University of Technology, Austria, in 1997, and the Dr.techn. degree from the Johannes Kepler University (JKU) in Linz, Austria, in 2001, for his work on first-generation direct-conversion transceivers for 3G.

From 2000 to 2011, he worked at Infineon Technologies as Director and Senior Principal Engineer, and from 2011 to 2019 at Intel as Senior Principal Engineer and Chief RF Technologist, contributing to several generations of cellular RF transceivers and mobile communications platforms, spanning from 2G to 5G, as analog circuit designer, project lead and RF systems architect. Since 2015 he has been a full professor heading the Institute for Integrated Circuits (IIC) at the JKU, Linz, where he is leading the Energy-Efficient Analog Circuits & Systems Group. Harald is a co-lead of the LIT/SAL mmWave Lab and the lead developer of the IIC-OSIC-TOOLS, an open-source IC design environment.

Harald Pretl was a member of the technical program committee of the ISSCC in 2010-2012 and has published more than 80 papers at international conferences and journals in the area of RF transceivers and analog circuits, in addition to more than 25 issued or filed patents. His current research interests are focused on cellular transceivers, wireless sensor networks, micro-power RF SoC for medical applications, and mm-wave circuits for 6G and advanced radar, as well as open-source IC design. He is a co-recipient of first place in the 2015 MTT-S PAWR student paper competition, the 2019 ReSMiQ best paper award at the IEEE NEWCAS conference, the 2019 APMC student prize, and a 2021 ISCAS best paper award. He is also a co-recipient of the Intel Achievement Award in 2019. He is a member of the Austrian Electrotechnical Association (OVE), the Association for Electrical, Electronic & Information Technologies (VDE), and the Silicon Austria Labs Advisory Board.

Amro Tork With 18 years of industrial experience in Fortune 500 companies like Intel, Samsung, and others,  Amro is AI and ML expert and an entrepreneur who founded Mabrains, a company that uses AI to advance EDA and chip design. Mabrains is focused on delivering high-quality software and consulting services for the chip design industry, leveraging advanced techniques in ML/DL such as  LLMs, embeddings, GANs, CNNs, RL, and unsupervised clustering. Amro published papers in IEEE conferences on topics such as reconfigurable spatial filtering, power distribution grid, and RF circuit design.

Akira Tsuchiya received his B.E., M.E. and Ph.D degrees in Communications and Computer Engineering from Kyoto University in 2001, 2003, and 2005, respectively. Since 2005, he has been an assistant professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. Since 2017, he has been an Associate Professor in the Department of Electronic Systems Engineering, The University of Shiga Prefecture, Shiga, Japan. His research interest includes CMOS analog/RF design and open-source IC design. He is one of the founders of an open-source IC community “ISHI-kai”.

Sadayuki Yoshitomi, Ph.D (IEEE member), joined TOSHIBA Research and Development Center, Kawasaki Kanagawa pref. Japan in 1993, where he is engaged in characterization and modeling of SiGe BiCMOS devices for RF applications. In 1999, he moved to the RF LSI design team of System LSI Division of TOSHIBA Corp, where he worked with the system design for GSM, Bluetooth applications. Since 2015, he is managing PDK development team for RF-CMOS application. He contributed PDK developments from 130nm to 40nm RF-CMOS as both manager and SPICE model engineer. From 2017 to 2022, he belonged to the memory division of TOSHIBA Corporation (currently named as KIOXIA corporation) as a chief specialist with the same role, where he contributed to the PDK developments of 3D Nand-Flash memory (BiCS) products. In 2022, he moved the ASIC design team of MegaChips corporation, Tokyo Japan, working with the highspeed ASIC design and next 5G system design. Dr.Sadayuki Yoshitomi is a subcommittee chair of BCICTS conference, TPC member of ESSDERC (EU), Mixdes (Poland) and IrPhe(Armenia) conferences, and working member of 79GHz license strategy working group of Japanese Interior Ministry.