Topology

  • No Comments

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS 150 150
Author(s): Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yong Chen

Abstract:

This article reports a 40-GS/s 8-bit time-interleaved (TI) time-domain (TD) gated-ring-oscillator analog-to-digital converter (GRO-ADC). An interleaving number of 32 is achieved with a single-channel 8-bit GRO-ADC operating at 1.25 GS/s, leading to a low front-end design complexity compared to recently published arts. The sampling front end employs a linearity-enhanced boosted …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671459
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS

A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS 150 150
Author(s): Nayu Li, Ziyao Xiong, Botao Yang, Hang Lu, Yiwei Liu, Xiaokang Qi, Gaopeng Chen, Na Yan, Chunyi Song, Zhiwei Xu

Abstract:

This article presents a K/Ka-band transmit/receive (T/R) front-end for jointed sensing and communication (JSAC) applications. A reconfigurable matching network for both signal reception and transmission is realized using the proposed triple-coupled transformer (TCT) technique, achieving low power loss and a compact footprint. The T/R switch at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667736
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS 150 150
Author(s): Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Abstract:

This article presents a fractional- ${ {N}}$ cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional- ${ {N}}$ reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652928
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Pseudo-Series Resonance CMOS Oscillator

A Pseudo-Series Resonance CMOS Oscillator 150 150
Author(s): Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski

Abstract:

This article presents a single-core, low-phase-noise (PN) digitally controlled oscillator (DCO) employing a pseudo-series resonance (pseudo-SR) technique with a transformer-based resonator. The proposed pseudo-SR resonator offers two key advantages: 1) a low impedance with a 180° phase shift at the impedance pole, emulating series resonance (SR) to enable single-stage oscillation and reduce …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663515
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications

A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications 150 150
Author(s): Pei Qin, Junyu Wu, Taotao Xu, Yongchun Li, Wenjie Feng, Quan Xue, Wenquan Che

Abstract:

This article presents a reconfigurable dual-path dual-band low noise amplifier (LNA) for fifth generation (5G) millimeter-wave (mmW) communications. A novel band-switching input matching architecture based on the cross-connected transistors is proposed to achieve optimal dual-band input matching and $g_{m}$ -boosting. This architecture allows the dual-band input transistors to share …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3661593
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Optimal Modulation Bits-to-RF Digital Transmitter Using Time-Interleaved Multi-Subharmonic Switching

An Optimal Modulation Bits-to-RF Digital Transmitter Using Time-Interleaved Multi-Subharmonic Switching 150 150
Author(s): Timur Zirtiloglu, Arman Tan, Basak Ozaydin, Ken R. Duffy, Muriel Médard, Rabia Tugce Yazicigil

Abstract:

This article presents a fully integrated bits-to-RF transmitter (Tx) featuring deep power back-off (PBO) enhancements, leveraging a multi-subharmonic switching (multi-SHS) digital power amplifier (DPA) with time-interleaving and a harmonic-rejection digital-to-phase converter (DPC). This work employs a nonuniform optimal modulation (OM) constellation, where symbol probability is inversely related to its amplitude, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3659903
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers

Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers 150 150
Author(s): Vinay Chenna, Hossein Hashemi

Abstract:

A topology optimization methodology is presented for the design of multistage, multipath, linear and nonlinear millimeter-wave (mm-Wave) power amplifiers (PAs). Optimization algorithms autonomously generate complete multilayered PA core layouts, including actives and passives, with minimal human intervention in just a few days. Experimental results from fabricated linear and nonlinear W-band …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3656334
Publisher: IEEE

View on IEEE Xplore

  • No Comments

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory 150 150
Author(s): Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu

Abstract:

This article presents SHINSAI—a 586 mm2 reusable active through-silicon via (TSV) interposer addressing key challenges in multi-chiplet integration (MCI) architectures. While active interposers overcome fundamental limitations of passive counterparts by integrating functional circuitry, existing solutions face three critical constraints: 1) non-recurring engineering (NRE) costs from application-specific interposers negating chiplet reuse benefits; 2) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 90 – 102
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623630
Publisher: IEEE

View on IEEE Xplore

  • No Comments

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter

3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 150 150
Author(s): Xiaosen Liu, Xichen Sun, Renwei Chen, Haozhe Zhang, Zhoutong Liu, Yan Wang

Abstract:

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 341 – 344
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3624096
Publisher: IEEE

View on IEEE Xplore

Search this website