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GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection 150 150
Author(s): Mao Li, Sanu K. Mathew, Vivek De, Mingoo Seok

Abstract:

This article presents GUARD, a fully digital, variation-tolerant detector for clock and voltage glitch attacks, featuring an integrated on-demand protection mechanism. Fabricated in 28-nm CMOS, GUARD provides robust security for digital systems by monitoring the system clock for maliciously injected faults. It employs a pair of optimized time-to-digital converters (TDCs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3696209
Publisher: IEEE

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A Cryogenic Superconducting Quantum Computing Unit Interface Chipset With Phase-Detection-Based Readout and Phase-Shifter-Based Controller

A Cryogenic Superconducting Quantum Computing Unit Interface Chipset With Phase-Detection-Based Readout and Phase-Shifter-Based Controller 150 150
Author(s): Yanshu Guo, Yaoyu Li, Wenqiang Huang, Tian Tian, Nan Wu, Siqi Zhang, Qichun Liu, Tiefu Li, Zhihua Wang, Ning Deng, Yuanjin Zheng, Hanjun Jiang

Abstract:

This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695612
Publisher: IEEE

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A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G

A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G 150 150
Author(s): Minzhe Tang, Dongfan Xu, Yi Zhang, Yuxuan Liu, Zheng Li, Yuncheng Zhang, Yilun Chen, Minghao Fan, Ziyuan Ren, Jian Pang, Dingxin Xu, Chenxin Liu, Daxu Zhang, Duo Li, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 21
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695546
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation

A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation 150 150
Author(s): Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Adiwena Putra, Jaehoon Heo, Joo-Young Kim

Abstract:

Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3689546
Publisher: IEEE

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A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

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QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC

QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC 150 150
Author(s): Minkyung Kim, Hyeongseok Seo, Songhyeon Kim, Jung-Hoon Chun, Seong-Jin Kim, Jaehyuk Choi

Abstract:

This article presents a high-resolution (HR) CMOS light detection and ranging (LiDAR) sensor capable of generating quarter video graphics array (QVGA) ( $320~{\times }~240$ ) depth images. To support high pixel density, the sensor employs a compact 6-transistor (6-T) nMOS-only single-photon avalanche diode (SPAD) analog front-end (AFE) with a column-shared active recharge circuit. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687569
Publisher: IEEE

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A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology

A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 150 150
Author(s): Mu Wu, Yihang Cheng, Xingli Cui, Sining Pan, Huaqiang Wu

Abstract:

This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 109 – 112
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3677301
Publisher: IEEE

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