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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A High-Voltage Symbol-Power-Tracking Supply Modulator for 5G GaN Power Amplifiers

A High-Voltage Symbol-Power-Tracking Supply Modulator for 5G GaN Power Amplifiers 150 150
Author(s): Changjin Chen, Minghao Shang, Yichao Ji, Qingqing Min, Chunyue Bo, Lin Cheng

Abstract:

This article presents a high-voltage symbol-power-tracking supply modulator (SPT-SM) that delivers a wide output range for 5G gallium nitride (GaN) power amplifiers (PAs). To enhance the output voltage transition speed, a two-step subranging dynamic voltage scaling (DVS) scheme and an inductor current slew-rate enhancement technique are proposed. By partitioning the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3731511
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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A 50-Gb/s Baud-Rate Burst-Mode Receiver Using a Phase Uncertainty Reduction Scheme Achieving 8-ns Phase Locking for 50G-PON in 28-nm CMOS

A 50-Gb/s Baud-Rate Burst-Mode Receiver Using a Phase Uncertainty Reduction Scheme Achieving 8-ns Phase Locking for 50G-PON in 28-nm CMOS 150 150
Author(s): Pingyi Cai, Xiongshi Luo, Ruixian Zhang, Kun Zhang, Wenhan Guan, Jiayao Li, Wenkang Luo, Yangyi Zhang, Quan Pan

Abstract:

This article presents a 50-Gb/s baud-rate burst-mode receiver (BMRX) for 50G-PON. A phase uncertainty reduction (PUR) scheme is proposed to narrow the maximum phase search range from 1 unit interval (UI) to 0.5 UI, thereby reducing the phase locking overhead while preserving low power consumption. To maintain robust burst acquisition across …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3728469
Publisher: IEEE

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A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement

A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement 150 150
Author(s): Junghwan Oh, Wiman Yoo, Dong-Kun Lee, Dong-Hyun Kim, Jong-Seok Kim

Abstract:

This article presents a 10-bit source-driver (SD) IC for high-resolution OLED-on-silicon (OLEDoS) microdisplays in augmented reality (AR)/virtual reality (VR) applications. To address the stringent constraints of aggressive area scaling, sub-microsecond settling time, and high output uniformity, three key techniques are proposed. First, a demultiplexer (DEMUX)-based channel width expansion …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726042
Publisher: IEEE

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An Eight-Channel Direct Analog Sensor Fusion Core for On-the-Spot Time-Series Analysis in Edge AI

An Eight-Channel Direct Analog Sensor Fusion Core for On-the-Spot Time-Series Analysis in Edge AI 150 150
Author(s): Jia-le Cui, Yasuko Matsubara, Yasushi Sakurai, Noriyuki Miura

Abstract:

A time-series analysis on multi-channel sensor signals is critical for wide-range Artificial Intelligence (AI) applications, such as in a field of mobility, robot, and infrastructure monitoring. Edge-device data collection followed by cloud-based analysis suffers from high latency and power consumption. This article presents an edge-AI-oriented sensor fusion architecture, performing analog …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726487
Publisher: IEEE

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Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback

Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback 150 150
Author(s): Luke D. Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn

Abstract:

Boolean satisfiability (SAT or $k$ -SAT, $k ge 3$ ) is a binary combinatorial optimization problem (COP) that is challenging for traditional classical computing to address in polynomial time. Quantum and quantum-inspired systems have been touted to tackle these and similar nondeterministic polynomial-time (NP) problems. This work describes Medusa, a quantum-inspired $k$ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726445
Publisher: IEEE

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A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support

A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support 150 150
Author(s): Boyang Cheng, Jianbo Liu, Steven Davis, Zephan M. Enciso, Likai Pei, Xueji Zhao, Muya Chang, Ningyuan Cao

Abstract:

The increasing demand for privacy-preserving personal data analytics in smart assistants and context-aware systems necessitates hardware that is both energy-efficient and secure. This work presents a 65 nm privacy-preserving neuromorphic encoder that addresses these challenges through physically uncloneable and hardware-efficient encoding. At the core of the architecture is a 2T–2T …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721817
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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