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Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback

Medusa: A Scalable Quantum-Inspired k-SAT Solver With Make and Break Feedback 150 150
Author(s): Luke D. Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn

Abstract:

Boolean satisfiability (SAT or $k$ -SAT, $k ge 3$ ) is a binary combinatorial optimization problem (COP) that is challenging for traditional classical computing to address in polynomial time. Quantum and quantum-inspired systems have been touted to tackle these and similar nondeterministic polynomial-time (NP) problems. This work describes Medusa, a quantum-inspired $k$ …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726445
Publisher: IEEE

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A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support

A 65 nm Privacy-Preserving Neuromorphic Encoder With 7.13 nJ Efficiency, 2.38 Mb/mm2 2T–2T Item Memory Density and Federated Learning Support 150 150
Author(s): Boyang Cheng, Jianbo Liu, Steven Davis, Zephan M. Enciso, Likai Pei, Xueji Zhao, Muya Chang, Ningyuan Cao

Abstract:

The increasing demand for privacy-preserving personal data analytics in smart assistants and context-aware systems necessitates hardware that is both energy-efficient and secure. This work presents a 65 nm privacy-preserving neuromorphic encoder that addresses these challenges through physically uncloneable and hardware-efficient encoding. At the core of the architecture is a 2T–2T …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721817
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3193 – 3207
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

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A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150
Author(s): Jiazhen Ni, Dayi Zhou, Minqing Cai, Chen Chen, Xiang Gao, Seung-Chul Lee

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

Published in: IEEE Solid-State Circuits Letters
Page(s): 214 – 217
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713349
Publisher: IEEE

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A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation

A Mixed-Signal SAT Solver for Exploring Nonideal Effects and Scalability in Analog Computation 150 150
Author(s): Ahmet Yusuf Salim, Soner Seçkiner, Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse

Abstract:

Recent years have seen growing interest in custom and nature-inspired computing methods for solving computationally challenging combinatorial optimization problems. The Boolean satisfiability (SAT), a canonical nondeterministic polynomial (NP)-complete problem, has remained a focal point due to its wide applicability in artificial intelligence, cryptography, and formal verification. This article presents …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3721413
Publisher: IEEE

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A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology

A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals ( $\phi _{0-5}$ ) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 194 – 197
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3707465
Publisher: IEEE

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