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A Clock-Edge Architecture for Processor Clock-Power Reduction

A Clock-Edge Architecture for Processor Clock-Power Reduction 150 150
Author(s): Yimai Peng, Daniel J. Yingling, Basma Hajri, Robert J. Vachon, Fikre Gebreyohannes, Vincent Li, Ghanshyam Chhetri, Keith A. Bowman

Abstract:

A clock-edge architecture (CEA), consisting of an adaptive clock duty-cycle controller (DCC), dual-edge-triggered (DET) flip-flops (FFs), and DET clock-gating circuits (CGCs), enables a processor to achieve the same performance as a conventional (CNV) design while operating at half the clock frequency (F ${}_{\mathrm {CLK}}$ ), thereby significantly reducing the clock power. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730222
Publisher: IEEE

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A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier

A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier 150 150
Author(s): Guo Wei, Rui Zhang, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This article presents a 14-bit 1-GS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) in a 28 nm CMOS process, targeting the optimization of conversion speed and latency. The implemented ADC adopts a two-stage architecture that integrates a residue amplifier (RA) assisted 4-bit/cycle sub-quantizer to tackle the accuracy bottleneck of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738437
Publisher: IEEE

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Probabilistic Computing With Neuromorphic Elements

Probabilistic Computing With Neuromorphic Elements 150 150
Author(s): Zonglong Li, Laurie E. Calvet

Abstract:

This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 167 – 175
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3712198
Publisher: IEEE

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One-Cycle-Balance Control in Buck Converters for Consecutive Load-Step Events

One-Cycle-Balance Control in Buck Converters for Consecutive Load-Step Events 150 150
Author(s): Zihao Tang, Jiacheng Yang, Rui P. Martins, Mo Huang

Abstract:

One-cycle-balance (OCB) response represents the optimal load-transient response for buck converters, maximizing system energy efficiency and robustness. While prior art has demonstrated OCB response for single load-step events, it fails in consecutive transients, which are prevalent in modern applications. This work overcomes these limitations by introducing an OCB controller that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 4975 – 4986
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3697453
Publisher: IEEE

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A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique

A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique 150 150
Author(s): Linran Zhao, Yiming Han, Yaoyao Jia

Abstract:

This article presents a low-power continuous-time (CT) $G_{mathrm {M}}$ -C-based $Delta Sigma $ analog-to-digital converter (ADC) employing capacitive input feedforward and a duty-cycled $G_{mathrm {M}}$ technique to enhance linearity while maintaining high energy efficiency. The ADC employs a CT capacitive network for concurrent signal summation and quantization, enabling input …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733305
Publisher: IEEE

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A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring

A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring 150 150
Author(s): Min-Hua Chang, Lin Chou, Yen-Jen Liu, Chen-Hsing Hsu, Ying-Yu Yang, Bo-Cheng Juan, Guan-Yu Lin, Yi-Jie Lin, Yao-Wei Huang, An-Ting Teng, Chun-Wei Chiu, Yi-Chen Hsiao, Yen-Yu Chen, Nitish Kumar, Shu-Ping Lin, Yu-Te Liao

Abstract:

A fully integrated multimodal biosensing system-on-chip (SoC) for stress monitoring is presented. The proposed SoC integrates electrocardiography (ECG), electrochemical (ECH), photoplethysmography (PPG), and galvanic skin response (GSR) sensing together with an on-chip transmitter (TX), wake-up receiver (WuRX), and power-management unit (PMU) for compact, standalone operation. ECG and ECH share a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3729275
Publisher: IEEE

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A Wide-Lock-in-Range and Fast-Settling-Time, 11.6-to-14-GHz SSPLL With an Event-Driven FLL and a Low-Power Harmonic-Lock Detector

A Wide-Lock-in-Range and Fast-Settling-Time, 11.6-to-14-GHz SSPLL With an Event-Driven FLL and a Low-Power Harmonic-Lock Detector 150 150
Author(s): Youngjun Kim, Siheon Lee, Taehyub Kim, Sunhaeng Heo, Younghyun Lim

Abstract:

This article presents a wide-lock-in-range and fast-settling-time, 11.6-to-14-GHz subsampling phase-locked loop (PLL) subsampling PLL (SSPLL) using an event-driven frequency-locked loop (ED-FLL) and a harmonic-lock detector (HLD). The ED-FLL becomes active only when a frequency disturbance, $f_{\mathrm {D}}$ , is detected, rapidly corrects the frequency error using a lock-expedition algorithm, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3729681
Publisher: IEEE

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A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry

A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry 150 150
Author(s): Zhenhao Li, Junyao Tang, Nawab Singh, Jianqiang Jiang, Lei Zhao, Wenshuo Zhu, Xuan Sun, Liang Dong, Cheng Huang

Abstract:

Existing single-link wireless power and data transfer (WPDT) systems for implantable biosensors support either closed-loop power regulation or sensor data uplink, but not both simultaneously, resulting in degraded efficiency and restricted sensing. This work presents a 13.56-MHz WPDT system with: 1) a synchronized phase-shifted time-multiplexed uplink scheme enabling TX power regulation …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730406
Publisher: IEEE

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A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification 150 150
Author(s): Hongjiang Chen, Jingxiang Wang, Kaize Zhang, Shizhan Mo, Liang Qi, Chao Zhao, Hao Zhang, Zhang Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730470
Publisher: IEEE

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