time-to-digital converter (TDC)

  • No Comments

A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System

A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System 150 150
Author(s): Siyuan Xu, Longhuang Li, Yiyang Du, Huiru Yang, Huaiyu Ye, Huan Hu

Abstract:

This article presents a pulse-width locked-loop (PWLL) time-domain readout integrated circuit (IC) for wearable strain-sensing systems based on a laser-induced graphene (LIG) strain sensor. A time-domain Wheatstone bridge (WhB) architecture is proposed, incorporating a duty-cycled resistor (DCR) and a voltage-controlled oscillator (VCO)-based integrator to realize a digitally intensive, energy-efficient, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704204
Publisher: IEEE

View on IEEE Xplore

  • No Comments

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection 150 150
Author(s): Mao Li, Sanu K. Mathew, Vivek De, Mingoo Seok

Abstract:

This article presents GUARD, a fully digital, variation-tolerant detector for clock and voltage glitch attacks, featuring an integrated on-demand protection mechanism. Fabricated in 28-nm CMOS, GUARD provides robust security for digital systems by monitoring the system clock for maliciously injected faults. It employs a pair of optimized time-to-digital converters (TDCs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3696209
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR

A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR 150 150
Author(s): Pooya Poolad, Foad Arvani, Bahaa Radi, Ping-Hsuan Hsieh, Tony Chan Carusone

Abstract:

We present a proof-of-concept light detection and ranging (LiDAR) signal processing architecture that integrates a machine-learning-enhanced processing unit (PU) with on-chip time-to-digital converters (TDCs) to reduce bandwidth and memory requirements in SPAD-based direct time-of-flight (dToF) systems. The proposed architecture fits a Gaussian mixture model (GMM) to photon arrival time distributions …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652972
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications 150 150
Author(s): Hsi-Hao Huang, Zong-Rui Cao, Ying-Ying Cheng, Jia-Yu Lin, Chen-Yi Lee

Abstract:

This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18- $\mu $ m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 41 – 44
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652323
Publisher: IEEE

View on IEEE Xplore

Search this website