System-on-chip

A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power

A 6.78-MHz Single-Stage Regulating Rectifier With Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131 mW Output Power 150 150

Abstract:

Targeting the wireless power transfer (WPT) to implantable medical devices (IMDs), this work presents a 6.78 MHz single-stage dual-output (SSDO) regulating rectifier. It can support the simultaneous charging of both outputs ( $V_{\text {OUT1}}$ and $V_{\text {OUT2}}$ , $V_{\text {OUT1}} \gt V_{\text {OUT2}}$ ) in a half cycle, rather than …

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A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems

A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems 150 150

Abstract:

This article proposes an envelope-tracking (ET) supply modulator (SM) that is scalable for sixth-generation (6G) communication systems. The design leverages a cost-efficient CMOS process for the power converters and a high-performance GaN process for the high-frequency power amplifier (PA) and the depletion-mode-only GaN-based amplifier. The proposed ET supply modulator (ETSM) …

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

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High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI

High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI 150 150

Abstract:

This article presents a high-precision close-to-analog programming methodology for phase-change memory (PCM) cells, targeting analog in-memory computing (AiMC) architectures for edge-artificial intelligence (AI) applications. By leveraging an iterative accumulation approach during the verify phase, the proposed technique enhances the effective number of bits (ENOBs) achievable in PCM cells. Experimental validation …

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An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control

An Ultralow Cross-Regulation Single-Inductor Multiple-Output (SIMO) Buck Converter Using Reordered Power-Distributive Control 150 150

Abstract:

A single-inductor multiple-output (SIMO) buck converter employing reordered power-distributive control (RPDC) is presented to achieve ultralow cross regulation. Adedicated power-distribution controller implements RPDC by adaptively adjusting the switching sequence: when the inductor current is insufficient, the switching period is extended, and when excessive, an end phase in the form of …

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A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference 150 150

Abstract:

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. …

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A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter

A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter 150 150

Abstract:

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a $100~000{\times }$ input power dynamic range (DR) (from $10~{\mu }$ W to 1W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. …

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A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception

A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception 150 150

Abstract:

This letter presents a multiband fully integrated ultralow-power (ULP) transceiver with a two-step wake-up receiver (WuRX) and switched-capacitor (SC)-based high-efficiency transmitter. Operating from 200 MHz to 1 GHz, the transceiver covers most IoT applications on a single chip. By employing a novel two-step wake-up scheme with a rotating correlator, the proposed …

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PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC

PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC 150 150

Abstract:

Compute-in-memory (CiM) accelerators perform matrix vector multiplications (MVMs) directly inside memory arrays, reducing data movement and improving both energy efficiency and throughput for artificial intelligence (AI) workloads. To reduce the number of conversions, recent designs use multibit compute cells. Nevertheless, practical multibit CiM still faces a tension among accuracy, efficiency, …

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