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Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 150 150
Author(s): Piyush Kumar, Da Eun Shim, Azad Naeemi

Abstract:

This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 139 – 147
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621279
Publisher: IEEE

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Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs 150 150
Author(s): Sadik Yasir Tauki, Rudra Biswas, Rakesh Acharya, Jiahui Duan, Rajiv Joshi, Kai Ni, Vijaykrishnan Narayanan

Abstract:

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 148 – 156
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619908
Publisher: IEEE

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Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model

Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model 150 150
Author(s): Mohammad Adnaan, Saeideh Alinezhad Chamazcoti, Emil Karimov, Marie Garcia Bardon, Francky Catthoor, Jan van Houdt, Azad Naeemi

Abstract:

We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM). We start with the ferroelectric capacitor device model and perform array-level memory circuit simulation. Then, we …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 99 – 106
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3618883
Publisher: IEEE

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A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories

A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories 150 150
Author(s): Jianze Wang, Wei Zhang, Xuanyao Fong

Abstract:

The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes, such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 123 – 130
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3616007
Publisher: IEEE

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A 1-8 GHz, 190MHz BB BW Mixer-First Receiver With Bootstrapped Mixer Switches Achieving Over 16dBm In-Band IIP3

A 1-8 GHz, 190MHz BB BW Mixer-First Receiver With Bootstrapped Mixer Switches Achieving Over 16dBm In-Band IIP3 150 150
Author(s): Erwin Hardeveld, Ronan van der Zee, Bram Nauta

Abstract:

In this article, we propose a wideband mixer-first receiver with improved in-band (IB) linearity. It uses bootstrapped N-path mixer switches to achieve a constant on-state gate–source voltage for large IB signals. We analyze the tradeoff between on-state resistance and off-state subthreshold current in conventional mixer switches and introduce a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3606117
Publisher: IEEE

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An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation

An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation 150 150
Author(s): Yongjia Li, Jianlin Xia, Feng Cheng, Yifan Cao, Jin Wu, Encheng Zhu, Xiaofeng Sun, Dejin Wang, Long Zhang, Zhongyuan Fang, Weifeng Sun

Abstract:

This letter presents an RC oscillator featuring a mixed-signal compensation loop that simultaneously mitigates comparator offset, loop delay, switch on-resistance, and temperature dependency. The oscillator employs an auxiliary comparator, a charge pump, and a differential difference amplifier (DDA)-based main comparator to suppress ramping voltage overshoots caused by device and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 333 – 336
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3615833
Publisher: IEEE

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A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time 150 150
Author(s): Haris Suhail, Haoran He, Vinod Kurian Jacob, Jiyue Yang, Kang L. Wang, Sudhakar Pamarti

Abstract:

Memory performance has emerged as a critical factor influencing both system speed and energy efficiency. However, conventional memory technologies such as embedded Flash (eFlash) and static RAM (SRAM) encounter significant scalability limitations beyond the 28-nm CMOS node. Among novel emerging memory technologies, spin-transfer-torque magnetic RAM (STT-MRAM) has gained prominence due …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3609342
Publisher: IEEE

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CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator

CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator 150 150
Author(s): Yuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang, Hóngyè Huáng, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Abstract:

Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611233
Publisher: IEEE

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A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range

A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range 150 150
Author(s): Jingyi Yuan, Qingqing Min, Siyang Liu, Lin Cheng

Abstract:

This article presents a wide-input-range buck converter featuring a conduction-loss-minimized zero-voltage switching (ZVS) technique. The proposed ZVS topology enables accurate ZVS operation across a wide range of input voltage ( $V_{\mathrm {IN}}$ ) and load current ( $I_{\mathrm {O}}$ ). By keeping the auxiliary inductor current pulse in the ZVS branch separate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3609411
Publisher: IEEE

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