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A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy

A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy 150 150
Author(s): Maryam Dodangeh, Mark S. Oude Alink, Jan Prummel, Bram Nauta

Abstract:

An ultralow-power Bluetooth low energy (BLE)-compliant crystal-less clock-harvesting receiver is presented that uses the BLE advertising packets (APs) to calibrate an on-chip frequency reference with ±400 ppm initial frequency offset. The proposed front-end, fabricated in 22 nm FDSOI, is capable of pushing the frequency accuracy of the reference further to below ±40/±15 …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718973
Publisher: IEEE

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A 28-nm Sign-Bit-Embedded Bit-Parallel SRAM Compute-in-Memory Macro With Stage-Wise-Enabled Transition-Counting-Lines and Accumulators for Edge-AI Devices

A 28-nm Sign-Bit-Embedded Bit-Parallel SRAM Compute-in-Memory Macro With Stage-Wise-Enabled Transition-Counting-Lines and Accumulators for Edge-AI Devices 150 150
Author(s): Yunlong Liu, Lichen Feng, Lin Wu, Dong Li, Zhangming Zhu

Abstract:

Computing-in-memory (CIM) architectures are promising for edge-AI devices, as they mitigate the von Neumann bottleneck and reduce data movement. Bit-parallel CIM macros with direct memory mapping and low toggle rate are well-suited for computing systems. However, severe routing congestion, inefficient signed computation, and unnecessary toggling of intermediate signals in local …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718075
Publisher: IEEE

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A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz

A 60-V High-Linearity Shunt-Based In-Line Current Sensor With DLL-Assisted Dynamic Body-Biasing and High dV/dt PWM Rejection Up to 2MHz 150 150
Author(s): Heng Ma, Huajun Zhang, Yuyan Liu, Qinwen Fan

Abstract:

This article presents a fully integrated shunt-resistor-based in-line current sensor for high-voltage (HV) pulse-width modulation (PWM)-based power systems. Floating-Gm current sensors are effective at rejecting HV PWM common-mode (CM) interference, but their linearity degrades at high CM voltages due to the substrate current-induced body effect (SCBE) in HV laterally …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3716767
Publisher: IEEE

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A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter

A Continuous-Time Incremental Zoom ADC With Extended Quantization, Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter 150 150
Author(s): Chaoyang Xing, Yilu Cui, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This article presents a continuous-time (CT) analog-to-digital converter (ADC) featuring an incremental zoom with extended quantization architecture. The proposed MASH topology comprises an 8-bit oversampled successive-approximation register (SAR) ADC as the first stage, a 1-bit incremental CT delta-sigma modulator (CT-DSM) as the second stage, and a 12-bit Nyquist SAR ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717666
Publisher: IEEE

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An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels

An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels 150 150
Author(s): Yoochang Kim, Seunghoon Yi, Seung Chae Jung, Hee-Cheol Joo, Young-Ha Hwang

Abstract:

This work presents an 11.5-Gb/s/pin transmitter (TX) for ultra-dense capacitively coupled channels that achieves near-complete eye-margin recovery while operating from a 0.4-V driver supply using a switched-coupling charge-pump-based crosstalk cancellation (SCCP-XTC) scheme. In the proposed scheme, one of four precharged capacitor banks in each XT cancellation (XTC) path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715082
Publisher: IEEE

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A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer

A 500-MS/s 94-dB-SFDR Resistive-Input Pipelined-SAR ADC With a Current-Buffer-Based Integrating Sampler and Floating Charge Transferrer 150 150
Author(s): Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This work presents a pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a current-buffer-based integrating sampler that combines an easy-to-drive resistive input with high linearity. To overcome the linearity and swing limitations of conventional current-integrating samplers (CISs), the frontend employs a $G_{m}$ -boosted continuous-time (CT) floating charge transferrer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3714848
Publisher: IEEE

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A Self-Powered 21-Component Transient Piezoelectric Energy Harvester With Single-Stage MPPT and Near-Zero Standby Consumption

A Self-Powered 21-Component Transient Piezoelectric Energy Harvester With Single-Stage MPPT and Near-Zero Standby Consumption 150 150
Author(s): Xiudeng Wang, Haohao Shi, Youlan Zeng, Libo Qian, Yang Liu, Guangqian Zhu, Yongyuan Li, Zhangming Zhu

Abstract:

This article presents a rectifierless synchronous inversion and optimal charge extraction (SIOCE) interface with single-stage maximum power point tracking (MPPT) for intermittent vibrations, which are common in real-world applications. Unlike conventional rectifiers that suffer from standby power consumption or rely on inefficient multi-stage conversion, the proposed SIOCE interface circuit decouples …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715865
Publisher: IEEE

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An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX

An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX 150 150
Author(s): Anoop Narayan Bhat, Erwin Allebes, Elbert Bechthum, Zule Xu, Stan van der Ven, Mohieddine El Soussi, Johan van Den Heuvel, Paul van Zeijl, Paul Mateman, Murat Eskiyerli, Stefano Traferro, Amirashkan Farsaei, Evgenii Tiurin, Sahan Gamage, Pepijn Boer, Igor Petrov, Jochem Govers, Huib Visser, Martijn Hijdra, Sharada Prasad Shantharam, Ivo Marques, Gururaja Kasanadi Ramachandra, Kaijie Ding, Ran Li, Aasish Boora, Peter Vis, Mario Konijnenburg, Arjan Breeschoten, Peng Zhang, Yao-Hong Liu, Christian Bachmann

Abstract:

This letter presents an 802.15.4ab/a/z compatible IR-UWB 2TRX highlighting a full-duplex-based radar, a semisynchronous TX and TRX’s digital baseband. A capacitive tuning technique proposed in the electrical balance duplexer (EBD)-based duplex RF front-end (RF-FE) improves TX-antenna insertion loss by 1.4 dB and the sensitivity of TX–RX …

Published in: IEEE Solid-State Circuits Letters
Page(s): 190 – 193
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697493
Publisher: IEEE

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Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150
Author(s): Sining Pan, Xiaohan Liu, Ziyi Li, Minge Jiang, Yihang Cheng, Zhong Tang, Huaqiang Wu

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711071
Publisher: IEEE

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