A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable timing over supply voltage. …