Receivers

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 150 150

Abstract:

This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied …

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A Real-Time Link-Adaptive 3-D Resonant Current-Mode Wireless Receiver With Self-Optimizing Control

A Real-Time Link-Adaptive 3-D Resonant Current-Mode Wireless Receiver With Self-Optimizing Control 150 150

Abstract:

This article presents a 3-D resonant current-mode wireless power receiver (RCM 3D-Rx) with autonomous optimum resonance cycle ( $N_{\mathrm {OPT}}$ ) detection and real-time link adaptivity for implantable medical devices (IMDs). The proposed design integrates three orthogonally oriented receiver coils within a com pact 3-D-printed PA12 structure, enabling orientation-insensitive power transfer …

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

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A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS 150 150

Abstract:

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits …

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A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS

A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS 150 150

Abstract:

This article presents a 436–472GHz four-element intermediate-frequency (IF) beamforming phased-array receiver fabricated in 65-nm CMOS, targeting scalable terahertz (THz) phased-array systems. The proposed receiver adopts a two-step mixing scheme to reduce the area overhead of the IF beamforming implementation, thereby enhancing the array scalability at THz frequencies. Each receive channel …

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A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI

A 6.3–18.4 GHz I/Q Receiver With RF and LO Path Reconfigurability for 6G FR3 Applications in 22-nm FD-SOI 150 150

Abstract:

This article presents a 6.3–18.4GHz in-phase and quadrature (I/Q) direct down-conversion receiver featuring reconfigurability in both the radio frequency (RF) and local oscillator (LO) paths. The receiver comprises a multi-band reconfigurable RF front-end, double-balanced passive I/Q mixers, an I/Q LO generation network with a tunable I/Q …

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A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G

A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G 150 150

Abstract:

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at …

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0.13 K NETD D-Band CMOS Passive Imager With Noise Suppression Analysis

0.13 K NETD D-Band CMOS Passive Imager With Noise Suppression Analysis 150 150

Abstract:

This article presents a new system design and in-depth analysis of a wideband, low-power passive imaging receiver based on a Dicke-switch architecture, implemented in 28 nm CMOS technology. The proposed structure employs a three-coil gm-boosting technique for the low-noise amplifier (LNA). This approach reduces the LNA’s noise figure (NF) and …

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A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer

A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer 150 150

Abstract:

This article introduces a hybrid Slepian beamforming receiver architecture with low power and area costs. Traditional large-scale true-time-delay (TTD) beamformers for wideband wireless communication suffer from high power consumption and high hardware costs. As an alternative, the Slepian beamforming approach reduces the number of analog-to-digital conversions (ADCs) and delays for …

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