Quantization (signal)

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A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression

A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression 150 150
Author(s): Chenyang Li, Tzu-Han Wang, Dongsuk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh S. Sathe, Shaolan Li

Abstract:

This article presents a two-step incremental analog-to-digital converter (ADC) that achieves high resolution and energy efficiency while substantially easing the input driving constraints and interstage gain variation. By employing a level-shifted sub-ranging architecture with an input-tracking (IT) feature, the design obviates direct input sampling, thereby significantly relaxing the demands on …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 884 – 897
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3635146
Publisher: IEEE

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TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes

TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes 150 150
Author(s): Harshit Naman, Gourab Barik, Yudhajit Ray, Shreyas Sen

Abstract:

Always-on, high-quality video sensors are increasingly required in wearables, surveillance, and Internet-of-Things (IoT) devices, where stringent energy constraints make efficient in-sensor compression necessary. These systems must support high-definition (HD) and 4 K video, yet conventional digital video compression pipelines consume significant power because high-speed analog-to-digital converters (ADCs) must digitize every pixel, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712196
Publisher: IEEE

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration

A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a low-spur, low-jitter fractional-N digital phase-locked loop (DPLL) employing an analog pre-distortion digital-to-time converter (APD-DTC) to suppress fractional spurs by compensating for both second- and third-order nonlinearities without using complex digital pre-distortion. To support background calibration, a spur-level detection scheme using phase detector gain (PDG) is proposed …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706350
Publisher: IEEE

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ASAP: A 28-nm Transformer Training Accelerator With Alternating Sparsity and Asymmetrical Microscaling Precision

ASAP: A 28-nm Transformer Training Accelerator With Alternating Sparsity and Asymmetrical Microscaling Precision 150 150
Author(s): HanGyeol Mun, Jian Meng, Xiaofeng Hu, Yuan Liao, Chun-Ting Chen, Jae-sun Seo

Abstract:

This work presents ASAP, a 28-nm transformer-training accelerator that combines N:M structured sparsity with asymmetric microscaling floating-point (MXFP) precision through a unified algorithm–hardware co-design. ASAP introduces a progressive sparsity schedule in which pruned compute resources are reassigned to increase numerical precision for important weights and activations, stabilizing optimization …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693653
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation

A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation 150 150
Author(s): Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Adiwena Putra, Jaehoon Heo, Joo-Young Kim

Abstract:

Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3689546
Publisher: IEEE

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A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization 150 150
Author(s): Hao Xu, Yizhuo Wang, Ziyang Jiao, Guoyu Li, Yiyun Mao, Shuai Liu, Yan Liu, Jimiao Sang, Qi Guo, Long Kong, Na Yan

Abstract:

A fractional-N digital phase-locked loop employs a novel analog-to-digital converter (ADC)-based phase detector (PD) to achieve direct phase digitization, thereby eliminating the need for a digital-to-time converter (DTC). The high PD gain reduces in-band phase noise, while its high linearity enables all-digital $\Sigma \Delta $ quantization noise cancellation. Implemented with …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671094
Publisher: IEEE

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An Electrophysiology-Optogenetics Closed-Loop Bi-Directional Neural Interface for Sleep Regulation With 0.2-μJ/class Multiplexer-Based Neural Network

An Electrophysiology-Optogenetics Closed-Loop Bi-Directional Neural Interface for Sleep Regulation With 0.2-μJ/class Multiplexer-Based Neural Network 150 150
Author(s): Chao Zhang, Fenyan Zhang, Dawid Sheng, Zhixiong Ma, Yongxiang Guo, Chao Sun, Yuwei Zhang, Wenxin Zhao, Xing Sheng, Tongfei A. Wang, Milin Zhang

Abstract:

This work proposed a multiplexer-based neural network (MUXnet), a multiplexer-based, multiplier-free neural network (NN) structure applicable to the implementation of all inner product-based NN layers. An on-chip MUXnet-based neural signal processing unit (NSPU) was designed, achieving a state-of-the-art accuracy of 82.4% on a public human sleep staging dataset, with the lowest …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3639446
Publisher: IEEE

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