Quantization (signal)

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A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling 150 150
Author(s): Dong-Hun Lee, Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Abstract:

This article introduces a high-resolution continuous-time delta–sigma modulator (CT DSM) architecture that incorporates a successive approximation register (SAR)-assisted digital noise coupling (DNC) technique and a multi-stage noise-shaping (MASH) structure. The limited maximum stable amplitude (MSA) problem due to the high-order-shaped large quantization error ( $Etextsubscript{1}$ ) in the previous …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3391902
Publisher: IEEE

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A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis 150 150
Author(s): Ruoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Binbin Yuan, Huazhong Yang, Yongpan Liu

Abstract:

BSTcontrol As neural network (NN) training cost red has been growing exponentially over the past decade, developing high-speed and energy-efficient training methods has become an urgent task. Fine-grained mixed-precision low-bit training is the most promising way for high-efficiency training, but it needs dedicated processor designs to overcome the overhead in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3377292
Publisher: IEEE

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Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications
Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications 150 150
Author(s): Jonah Van Assche, Georges Gielen

Abstract:

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3373553
Publisher: IEEE

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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array
A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 150 150
Author(s): Injune Yeo, Wangxin He, Yuan-Chun Luo, Shimeng Yu, Jae-Sun Seo

Abstract:

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 70 – 73
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3361011
Publisher: IEEE

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A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques
A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques 150 150
Author(s): Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Sijun Du, Bo Zhao

Abstract:

The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 702 – 715
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2023.3344587
Publisher: IEEE

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