Power demand

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Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro 150 150
Author(s): Bastien Giraud, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas

Abstract:

This article presents a comprehensive assessment of the impact of various design assist techniques on the inherent performance and reliability of native resistive RAM (RRAM) on silicon. The collaborative optimization of design and technology plays a crucial role in replacing conventional flash memory as the leading solution. We showcase that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3386429
Publisher: IEEE

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A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS

A 2 $\times$ 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS 150 150
Author(s): Liping Zhong, Hongzhi Wu, Weitao Wu, Catherine Wang, Wenbo Xiao, Xiongshi Luo, Yangyi Zhang, Dongfan Xu, Wei Wang, Taiyang Fan, Zhenghao Li, Xuxu Cheng, Quan Pan

Abstract:

A 2 $times$ 56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active crosstalk extraction (A-XTCR) is proposed to improve the signal reutilization efficiency of the RX. By …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3387355
Publisher: IEEE

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A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET 150 150
Author(s): Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo

Abstract:

A digital-to-analog converter (DAC)-based polar transmitter (TX) is proposed for multicarrier signaling in wireline applications. The proposed TX achieves a 50-Gb/s total data rate with maximized spectral efficiency by using three parallel 5-GS/s DAC-based drivers and two orthogonal carriers of 5 and 10 GHz. The three DAC-based drivers operating …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3376079
Publisher: IEEE

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A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA

A 300- $\mu$ W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA 150 150
Author(s): Martin Lee, Motaz Mohamed Elbadry, Kambiz Moez

Abstract:

This article introduces a novel ultra-low-power reference-based low-noise amplifier (LNA) designed to reduce performance variations due to process, voltage, and temperature (PVT) when operating in the subthreshold region. The LNA is embedded within a reference circuit that directly controls the performance of the LNA over PVT variations. By combining the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3375154
Publisher: IEEE

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Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications

Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications 150 150
Author(s): Jonah Van Assche, Georges Gielen

Abstract:

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3373553
Publisher: IEEE

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A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems

A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems 150 150
Author(s): Pierre-François Rüedi, Riccardo Quaglia, Hans-Rudolf Graf

Abstract:

We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc …

Published in: IEEE Solid-State Circuits Letters
Page(s): 106 – 109
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3370797
Publisher: IEEE

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A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators 150 150
Author(s): Martijn Timmermans, Kyle van Oosterhout, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore

Abstract:

This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1194 – 1203
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3352735
Publisher: IEEE

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A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques

A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques 150 150
Author(s): Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Sijun Du, Bo Zhao

Abstract:

The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 702 – 715
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2023.3344587
Publisher: IEEE

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