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A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer

A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer 150 150
Author(s): Zhengqi Xu, Zhiyuan Zhao, Michael A. Laun, Coleman DeLude, Justin Romberg, Michael P. Flynn

Abstract:

This article introduces a hybrid Slepian beamforming receiver architecture with low power and area costs. Traditional large-scale true-time-delay (TTD) beamformers for wideband wireless communication suffer from high power consumption and high hardware costs. As an alternative, the Slepian beamforming approach reduces the number of analog-to-digital conversions (ADCs) and delays for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651452
Publisher: IEEE

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A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications 150 150
Author(s): Hsi-Hao Huang, Zong-Rui Cao, Ying-Ying Cheng, Jia-Yu Lin, Chen-Yi Lee

Abstract:

This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18 μm HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the entire sensing …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652323
Publisher: IEEE

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An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver

An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver 150 150
Author(s): Youssef O. Hassan, Mohammad Oveisi, Zisong Wang, Payam Heydari

Abstract:

A CMOS 100–140-GHz end-to-end receiver (RX) is presented that integrates the antenna input all the way to the bitstream output, while demodulating 64QAM/16QAM/QPSK entirely in the analog domain. A sequential asynchronous demodulation method enables 120-Gbps operation at a notably small baseband power consumption. Fabricated in a 22-nm FDSOI …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648748
Publisher: IEEE

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An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators

An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators 150 150
Author(s): Ritaro Takenaka, Tetsuya Iizuka

Abstract:

This article proposes a 14-bit, 560-MS/s subranging analog-to-digital converter (ADC) that employs an amplifier-switching architecture with multi-threshold comparators. The proposed amplifier-switching architecture reuses a flash quantizer multiple times during subranging conversion by amplifying the residue voltage with an appropriate gain at each quantization step. This approach reduces the required …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3647024
Publisher: IEEE

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Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles

Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles 150 150
Author(s): Junyi Qian, Lishuo Deng, Cai Li, Yizhi Ding, Weiwei Shan

Abstract:

Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this …

Published in: IEEE Solid-State Circuits Letters
Page(s): 25 – 28
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3645701
Publisher: IEEE

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A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode

A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode 150 150
Author(s): Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a high-density (HD) 6T SRAM macro designed in 3-nm FinFET technology with an extended dual-rail (XDR) architecture, addressing active energy and leakage for mobile applications. Two key innovations are introduced: the delayed-wordline in write operation (DEWL) technique and a one-cycle latency low-leakage access mode (1-CLM). The XDR …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3639747
Publisher: IEEE

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A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN

A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN 150 150
Author(s): Mamoru Sato, Sachio Akebono, Kazuyoshi Yasuoka, Eriko Kato, Masahiro Tsuruta, Chiaki Takano, Kensuke Ota, Kazuki Haraguchi, Masahiro Watanabe, Genki Fujii, Koichiro Yamanaka, Kazunori Yasuda, Satoshi Minami, Katsuhiko Hanzawa, Kohei Matsuda, Akihiko Kato, Yosuke Ueno

Abstract:

This letter presents a CMOS image sensor (CIS) that integrates two operation modes: 1) a high-resolution viewing mode with $0.8~\mu $ m 32 Mpixels and 2) a low-power always-on object recognition mode consuming 2.67 mW at 10 frames/s. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An …

Published in: IEEE Solid-State Circuits Letters
Page(s): 353 – 356
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628314
Publisher: IEEE

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A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology

A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology 150 150
Author(s): Ethan Chou, Hesham Beshary, Nima Baniasadi, Ali M. Niknejad

Abstract:

This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 349 – 352
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3626442
Publisher: IEEE

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A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source

A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source 150 150
Author(s): Xinjie Wu, Xiaopeng Yu, Nick Nianxiong Tan, Zhong Tang

Abstract:

This work presents a 14-bit energy-efficient bandwidth (BW)/power scalable continuous-time delta–sigma modulator (CTDSM) for sensor interfaces in IoT applications. To ensure low noise for small input signals and achieve BW/power scalability, it is built around Gm-C integrators biased via a linear frequency-controlled current source (FCCS). The FCCS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621527
Publisher: IEEE

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