Power demand

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A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming

A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming 150 150
Author(s): Changde Ding, Yan Zhu, Pengjie Wang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully-digital beamforming in endoscopic and catheter-based 3D-ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20 MS/s SAR ADC. To minimize chip area …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581584
Publisher: IEEE

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A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique

A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique 150 150
Author(s): Sungjin Kim, Jeonghyun Lee, Yoonse Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon

Abstract:

This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 177 – 180
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578546
Publisher: IEEE

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A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations 150 150
Author(s): Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

Abstract:

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit $2times $ reference frequency multiplication. The design includes a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1368 – 1383
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3535888
Publisher: IEEE

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A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface 150 150
Author(s): Jing Wang, Jun He, Man-Kay Law, Xinzhe Wang, Futian Liang, Lin Cheng

Abstract:

This work proposes a temperature and process-compensated low-power Cryo-CMOS voltage reference without trimming for quantum integrated interface, which is capable of operating continuously from room temperature (RT) down to cryogenic temperatures. By compensating for the main accuracy limiting factors including the process dependence of the transistor threshold voltage, device mismatch …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3242 – 3256
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3530472
Publisher: IEEE

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A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation

A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation 150 150
Author(s): Rundi Wu, Yetong Wang, Ran Hong, Zongle Ma, Kenan Xie, Fanyi Meng, Kaixue Ma, Keping Wang

Abstract:

This article presents a mixer-first blocker-tolerant receiver (RX) with effective switch resistance ( ${R} _{\text {SW}}$ ) compensation and high-Q selectivity. By analyzing the impact of non-ideal 1/N LO duty cycle and effective ${R} _{\text {SW}}$ on mixer-first RX, an effective ${R} _{\text {SW}}$ compensation technique is proposed to mitigate noise figure (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1554 – 1569
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529681
Publisher: IEEE

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A Multi-Core Series-Resonance CMOS Oscillator

A Multi-Core Series-Resonance CMOS Oscillator 150 150
Author(s): Shiwei Zhang, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi

Abstract:

Multi-core and series-resonance (SR) techniques have been proposed to achieve ultra-low phase noise (PN) performance. In this article, a scalable ring-coupling scheme is proposed for multi-core expansion. The mechanism provides intrinsic oscillation and PN reduction without compromising the passive network, specifically tailored for the SR oscillator. The dual closed ring …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1644 – 1655
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3529600
Publisher: IEEE

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